Using DSP Algorithms for CRC in a CAN Controller

  • Juan, Ronnie O. Serfa ;
  • Kim, Hi Seok
  • Received : 2016.02.16
  • Accepted : 2016.02.24
  • Published : 2016.02.29


A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.


Parallel CRC;Pipelining;Retiming;Unfolding;CRC-15


  1. P. Koopman. (2002). 32-bit Cyclic Redundancy Codes for Internet Applications. Proc. IEEE International Conference on Dependable Systems and Networks.
  2. FlexRay Consortium. (2010, October). FlexRay Communication System Protocol Specification Version 3.0.1 pp. 114-115.
  3. BOSCH. (2012, April). CAN with Flexible Data-Rate Specifications pp. 12-13.
  4. W. Voss, "Error Detection and Fault Confinement," in A Comprehensible Guide to Controller Area Network, 2nd ed., Copperhill Media Corporation, 2008, pp. 117-122.
  5. Ch. Janakiram, and K.N.H. Srinivas, (2014, December). An Efficient Technique for Parallel CRC Generation. International Journal of engineering and Computer Science. pp. 9761-9765.
  6. O. Pfeiffer, A. Ayre, and C. Keydel, "Underying Technology: CAN", in Embedded Netwroking with CAN and CANopen, Copperhill Technologies Corporation, 2008, pp.
  7. W. W. Peterson, and D. T. Brown, "Cyclic Codes for Error Detection," in Proc. IRE, 1961, pp. 228-235.
  8. M. Ayinala, and K. K. Parhi (2011, September). High-Speed Parallel Architectures for Linear Feedback Shift Registers. IEEE Transactions on Signal Processing. 59(9), pp. 4459-4469.
  9. T. Zhang, and Q. Ding. (2011, December). Design and Implementation of CRC Based on FPGA. IEEE 2nd International Conference in Innovations in Bioinspired Computing and Applications (IBICA). pp. 160-162.
  10. B. N. Reddy, B. K. Kumar, and K. M. Sirisha, (2012). On the Design of High Speed Parallel CRC Circuits using DSP Algorithms. International Journal of Computer Science and Information Technologies (IJCSIT). pp. 5254-5258.
  11. C. Cheng, and K. K. Parhi, (2006, October). High- Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming. IEEE Transactions on Circuits and Systems. pp. 1017-1021.
  12. S. Singh, S. Sujana, I. Babu and K. Latha, (2013, May-June). VLSI Implementation of Parallel CRC Using Pipelining, Unfolding and Retiming. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP). pp. 66-72.


Grant : Development of Smart Automotive ADAS SW-SoC for Self-Driving Car

Supported by : Ministry of Trade, Industry and Energy