A Continuous Fine-Tuning Phase Locked Loop with Additional Negative Feedback Loop

추가적인 부궤환 루프를 가지는 연속 미세 조절 위상 고정루프

Choi, Young-Shig

  • Received : 2016.01.07
  • Accepted : 2016.03.11
  • Published : 2016.04.30


A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.


PLL;Continuous Band-selection;Two Negative Feedback Loops;Phase Noise


  1. Floyd M. Gardner, "Charge-Pump Phase-Lock Loop," IEEE J. Tran, on Communications, vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
  2. K. Lim, C. Park, D. Kim and B. Kim, "A Low-Noise Phase-Locked Design by Loop Bandwidth Optimization," IEEE J. solid state circuits, vol. 35, no. 6, pp. 807-815, June 2000.
  3. Mozhgan Mansuri and Chih-Kong Ken Yang, "Jitter Optimization Based on Phase-Locked Loop Design Parameters," IEEE J. solid state circuits, vol. 37, no. 11, pp. 1375-1382, Nov. 2002.
  4. J. Oehm and D. Pham-Stabner, "Linear Controlled Temperature Independent Varactor Circuitry," in Proc. 28th Eur. Solid-State Circuits Conf., Sep. 2002, pp. 143-146.
  5. B. Hanafi and E. Hegazi, "A Technique for Truly linear LC VCO Tuning, a Proof of Concept," in Proc. Int. Conf. Microelectron., pp. 93-146, Dec. 2007.
  6. Y. Tokunaga, S. Sakiyama, A. Matsumoto and S. Dosho, "An On-Chip CMOS Relaxation Oscillator with Voltage Averaging Feedback," IEEE J. solid state circuits, vol. 45, no. 6, pp. 1150-1158, Jun. 2010.
  7. A. A. Abidi, "Linearization of Voltage-Controlled Oscillators using Switched Capacitor Feedback," IEEE J. solid state circuits, vol. 22, no. 3, pp. 494-496, Jun. 1987.
  8. M. Youssef, A. Zolfaghari, H. Darabi and A. A. Abidi, "A Low-Power Wideband Polar Transmitter for 3G Applications," in IEEE ISSCC Dig. Tech. Papers, pp. 378-380, 2011.
  9. M. Youssef, A. Zolfaghari, B. Mohammadi, H. Darabi and A. A. Abidi, "A Low-Power Wideband Polar Transmitter in 65-nm CMOS," IEEE J. solid state circuits, vol. 46, no. 12, pp. 3061-3074, Dec. 2011.
  10. S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, "A 90-nm CMOS 5-GHz Ring-Oscillator PLL with Delay-Discriminator-based Active Phase-Noise Cancellation," IEEE J. solid state circuits, vol. 48, no. 5, pp. 1151-1160, May 2013.
  11. W. B. Wilson, Un-Ku Moon, K. R. Lakshmikumar and L. Dai, "A CMOS self-calibrating frequency synthesizer," IEEE J. Solid-State Circuits, vol.35, no.10, pp.1437-1444, Oct. 2000.
  12. H.I. Lee, J.K. Cho, K.S. Lee, I.C. Hwang, T.W. Ahn, K.S. Nah and B.H. Park, "A ${\Delta}{\Sigma}$ fractional-N frequency synthesizer using a wide band integrated VCO and a fast AFC technique for GSM/GPRS/WCDM applications," IEEE J. Solid-State Circuits, vol.39, no.7, pp.1164-1169, Jul. 2004
  13. T. H. Lin and W. J. Kaiser, "A 900-MHz 2.5mA CMOS frequency synthesizer with an automatic SC tuning loop," IEEE J. Solid-State Circuits, vol.36, no.3, pp.424-431, Mar. 2001.
  14. Y.W. Chen, Y.H. Yu and Y.J. Emery Chen, "A 0.18-${\mu}m$ CMOS dual-band frequency synthesizer with spur reduction calibration," IEEE Microwave and wireless components letters, vol.23, no.10, pp. 551-553, Oct. 2013.
  15. T. H. Lin and Y. J. Lai, "Am agile VCO frequency calibration technique for a 10-GHz CMOS PLL," IEEE J. Solid-State Circuits, vol. 42, no.2, pp. 340-349, Feb. 2007.
  16. J. S. Shin and H. C. Shin, "A 1.9-3.8 GHz ${\Delta}{\Sigma}$ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency," IEEE J. Solid-State Circuits, vol.47, no.3, pp. 665-675, March. 2012.
  17. Y-G. Song, Y. S. Choi and J-G Ryu, "A phase-locked loop of the resistance and capacitance scaling scheme with multiple charge pump," Analog Integr. Circ. Sig. Process, vol. 66, no. 2, 155-162, Feb. 2011.
  18. J. H. Nam, Y. S. Choi and M. G. Joo, "A single capacitor loop filter phase-locked loop with frequency voltage converter," Analog Integr. Circ. Sig. Process, vol. 74, no. 1, pp. 193-201, Jan. 2013.
  19. Young-Shig Choi, "A Negative Feedback Looped Voltage-Controlled Ring Oscillator with Frequency Voltage Converter," IEEE Trans. Microwave theory and techniques, vol. 61, no. 9, pp. 3271-3276, Sept. 2013.


Supported by : Pukyong National University