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Design of Dual loop PLL with low noise characteristic

낮은 잡음 특성을 가지기 위해 이중 루프의 구조를 가지는 위상고정루프 구현

  • Received : 2016.01.14
  • Accepted : 2016.02.25
  • Published : 2016.04.30

Abstract

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

Keywords

PLL;Continuous Band-selection;Two Negative Feedback Loops;Phase Noise

References

  1. D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, "A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver," IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1606-1617, Jul. 2011. https://doi.org/10.1109/JSSC.2011.2143950
  2. Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, and M.-C. F. Chang, "A 70-78-GHz integrated CMOS frequency synthesizer for-band satellite communications," IEEE Trans. Microw. Theory Tech, vol.59, no. 12, pp. 3206-3218, Dec. 2011. https://doi.org/10.1109/TMTT.2011.2168972
  3. R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, "A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-mm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, Nov. 2004. https://doi.org/10.1109/JSSC.2004.835833
  4. Marianne M. Kamal, Emad W. El-Shewekh, and Muhammad H. EL-SABA, "Design and implementation of a low-phase-noise integrated CMOS Frequency Synthesizer for high - sensitivity narrow-band FM transceivers," Microelectronics, pp.167-175, Cairo, Egypt. Dec. 2003.
  5. H.Y Chang, Y.L Yeh, Y.C Liu, M.H Li, K. Chen, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology," IEEE Trans. Microw. Theory Techn., vol. 62, No. 3, pp 543-555, March 2014. https://doi.org/10.1109/TMTT.2014.2302747
  6. Youn-Gui Song, Young-Shig Choi and Ji-Goo Ryu, "A phase locked loop with resistance and capacitance scaling scheme," IEEK SD, vol. 46, no. 4, pp. 37-44, Apr. 2009.
  7. Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim and Beomsup Kim, "A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 807-815, June 2000. https://doi.org/10.1109/4.845184
  8. Tsung-Hsien Lin and William J. Kaiser, "A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, March 2001. https://doi.org/10.1109/4.910481
  9. Shen Ye, Lars Jansson and Ian Galton, "A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, December 2002. https://doi.org/10.1109/JSSC.2002.804339
  10. J.Luo, Lei Zhang, Li Zhang, Y. Wang, Z. Yu, "A 24GHz low power and low phase noise PLL frequency synthesizer with constant Kvco for 60GHz wireless applications," Circuits and Systems IEEE, pp. 2940-2543, October 2015.
  11. Youn-Gui Song, Young-Shig Choi and Ji-Goo Ryu, "A fast locking Phase Locked Loop with multiple charge pumps", IEEK SD, vol 46, Feb. 2009.

Acknowledgement

Supported by : Daejeon University