General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors

DOI QR코드

DOI QR Code

Najam, Syed Faraz;Tan, Michael Loong Peng;Yu, Yun Seop

  • 투고 : 2016.03.10
  • 심사 : 2016.04.29
  • 발행 : 2016.06.30

초록

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters Ak and Bk, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (Ids-Vgs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

키워드

Compact model;Drain current;Inverter;Potential profile;TFET;Verilog

참고문헌

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과제정보

연구 과제번호 : 반도체공정장비

연구 과제 주관 기관 : 한경대학교산학협력단