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A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches

Edwin Jose, S.;Titus, S.

  • Received : 2015.12.21
  • Accepted : 2016.03.10
  • Published : 2016.07.20

Abstract

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

Keywords

Component count;Level dependent sources concoction multilevel inverter (LDSCMLI);Phase disposition pulse width modulation

References

  1. N. S. Choi, J. G. Cho, and G. H. Cho, “A general circuit topology of multilevel inverter,” Proceedings of 22nd Annual IEEE Power Electronics Specialists Conference (PESC’91), pp. 96-103, 1991.
  2. K. Corzine and Y. Familiant, “A new cascaded multilevel H-bridge drive,” IEEE Trans. Power Electron., Vol. 17, No. 1, pp. 125-131, Jan. 2002. https://doi.org/10.1109/63.988678
  3. B. P. McGrath and D. G. Holmes, “Natural capacitor voltage balancing for a flying capacitor converter induction motor drive,” IEEE Trans. Power Electron., Vol. 24, No.6, pp. 1554-1561, Jun. 2009. https://doi.org/10.1109/TPEL.2009.2016567
  4. J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 724-738, Aug. 2002. https://doi.org/10.1109/TIE.2002.801052
  5. A. L. Batschauer, S. A. Mussa, and M. L. Heldwein, “Three-phase hybrid multilevel inverter based on half-bridge modules,” IEEE Trans. Ind. Electron., Vol. 59, No. 2, pp. 668-678, Feb. 2012. https://doi.org/10.1109/TIE.2011.2158039
  6. E. Babaei, “A cascade multilevel converter topology with reduced number of switches,” IEEE Trans. Power Electron., Vol. 23, No. 6, pp. 2657-2664, Nov. 2008. https://doi.org/10.1109/TPEL.2008.2005192
  7. J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications,” IEEE Trans. Power Electron., Vol. 26, No. 11, pp. 3109-3118, Nov. 2011. https://doi.org/10.1109/TPEL.2011.2148177
  8. A. Nami, F. Zare, A. Ghosh and F. Blaabjerg, “A hybrid cascaded converter topology with series-connected symmetrical and asymmetrical diode-clamped H-bridge cells,” IEEE Trans. Power Electron., Vol. 26, No. 1, pp. 51-64, Jan. 2011. https://doi.org/10.1109/TPEL.2009.2031115
  9. M. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology for drive application,” Proceedings of Applied Power Electronics Conference (APEC'98), pp. 523-529, 1998.
  10. A. Rufer, M. Veenstra, and K. Gopakumar, “Asymmetric multilevel converter for high resolution voltage phasor generation,” Proceedings of European Power Electronics Conference (EPE'99), 1999.
  11. G. J. Su, “Multilevel dc-link inverter,” IEEE Trans. Ind. Appl., Vol. 41, No. 3, pp. 848-854, May/Jun. 2005. https://doi.org/10.1109/TIA.2005.847306
  12. S. Ramkumar, V. Kamaraj, S. Thamizharasan, and S. Jeevananthan, “A new series parallel switched multilevel dc-link inverter topology,” International Journal of Electrical Power & Energy Systems, Vol. 36, No. 1, pp. 93-99, Mar. 2012. https://doi.org/10.1016/j.ijepes.2011.10.028
  13. E. Babaei, S. H. Hosseinia, G. B. Gharehpetianb, M. T. Haquea, and M. Sabahia, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology,” Elsevier Journal of Electric Power System Research, Vol. 77, No. 8, pp. 1073-1085, Jun. 2007. https://doi.org/10.1016/j.epsr.2006.09.012
  14. A. Lesnicar and R. Marquardt, “An innovative modular multilevel converter topology suitable for a wide power range,” Proceedings of IEEE Power Technical Conference, Vol. 3, 2003.
  15. G. P. Adam, O. Anaya-Lara, G. M. Burt, D. Telford, B. W. Williams, and J. R. Mcdonald, “Modular multilevel inverter: pulse width modulation and capacitor balancing technique,” IET Power Electronics, Vol. 3, No. 5, pp. 702-715, Sep. 2010. https://doi.org/10.1049/iet-pel.2009.0184
  16. K. K. Gupta and S. Jain, “Topology for multilevel inverters to attain maximum number of levels from given DC sources,” IET Power Electron,, Vol. 5, No. 4, pp. 1755-4535, Apr, 2012. https://doi.org/10.1049/iet-pel.2011.0178
  17. A. Ajami, M. R. J, Oskuee, M. T. Khosroshahi, and A. Mokhberdoran, “Cascade-multi-cell multilevel converter with reduced number of switches,” IET Power Electron., Vol. 7, No. 3, pp. 552-558, Mar. 2014. https://doi.org/10.1049/iet-pel.2013.0261
  18. M. T. Khosroshahi, A. Ajami, A. O. Mokhberdoran, and M. J. Oskuee, “Multilevel hybrid cascade-stack inverter with substantial reduction in switches number and power losses,” Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 22, No. 4, pp. 987-1000, Jun. 2015. https://doi.org/10.3906/elk-1304-179
  19. P. M. Bhagwat and V. R. Stefanovic, “Generalized structure of a multilevel PWM inverter,” IEEE Trans. Ind. Appl., Vol. 19, No. 6, pp. 1057-1069, Nov./Dec. 1983. https://doi.org/10.1109/TIA.1983.4504335
  20. G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A new multilevel PWM method: A theoretical analysis,” IEEE Trans. Power Electron., Vol. 7, No. 3, pp. 497-505, Jul. 1992. https://doi.org/10.1109/63.145137
  21. B. P. McGrath and D. G. Holmes, “A comparison of multi carrier PWM strategies for cascaded and neutral point clamped multilevel inverters,” Proceedings of 31st Annual IEEE Power Electronics Specialized Conference (PESC'2000), pp.674-679, 2000.
  22. M. Calais, L. J. Borle, and V. G. Agelidis, “Analysis of multi-carrier PWM methods for single-phase five level inverter,” Proceedings of 32nd Annual Meeting and IEEE Power Electronics Specialized Conference (PESC'2001), Vol. 3, pp. 1351-1356, 2001.
  23. H. Patangia and D. Gregory, “A class of optimal multilevel inverters based on sectionalized PWM (S-PWM) modulation strategy,” Proceedings of 52nd IEEE International Conference on Midwest Symposium on Circuits and Systems (MWSCAS'09), pp. 937-940, 2009.
  24. S. N. Rao, D. V. A. Kumar and C. S. Babu, “New multilevel inverter topology with reduced number of switches using advanced modulation strategies,” Proceedings of IEEE International Conference on Power, Energy and Control (ICPEC), pp. 693-699, 2013.
  25. M. Kanimozhi and P. Geetha, “A new boost switched capacitor multilevel inverter using different multi carrier PWM techniques,” Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 432-437, 2014.
  26. V. N. Nguyen and J. Y. Myung, “A Single Carrier Multi-Modulation Method In Multilevel Inverters,” Journal of Power Electronics, Vol. 5, No. 1, pp. 76-82, Jan. 2005.
  27. V. N. Nguyen and J. Y. Myung, “A unified carrier based PWM method in multilevel inverters,” Journal of Power Electronics, Vol. 5, No. 2, pp.142-150, Apr. 2005.
  28. S. Agarwal and S. R. Deore, “Level shifted SPWM of a seven level cascaded multilevel inverter for STATCOM applications,” Proceedings of IEEE International Conference on Nascent Technologies in the Engineering Field (ICNTE), pp. 1-7, 2015.
  29. S. Venkatanarayanan and M. Saravanan, “Implementation of sliding mode controller for Single Ended Primary Inductor Converter,” Journal of Power Electronics, Vol. 15, No. 1, pp. 39-53, Jan. 2015. https://doi.org/10.6113/JPE.2015.15.1.39
  30. S. Venkatanarayanan and M. Saravanan, “Design of parallel operated SEPIC converters using coupled inductor for sharing load,” Journal of Power Electronics, Vol. 15, No. 2, pp. 327-337, Mar. 2015. https://doi.org/10.6113/JPE.2015.15.2.327

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