A Hardware Design of Ultra-Lightweight Block Cipher Algorithm PRESENT for IoT Applications

IoT 응용을 위한 초경량 블록 암호 알고리듬 PRESENT의 하드웨어 설계

  • Received : 2016.03.30
  • Accepted : 2016.04.21
  • Published : 2016.07.31


A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.


Lightweight Block Cipher;PRESENT;IoT Security;Information Security;Symmetric Key Encryption


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Grant : Development of Main IPs for IoT and Image-Based Security Low-Power SoC

Supported by : Ministry of Trade, Industry & Energy