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NVM-based Write Amplification Reduction to Avoid Performance Fluctuation of Flash Storage

플래시 스토리지의 성능 지연 방지를 위한 비휘발성램 기반 쓰기 증폭 감소 기법

  • 이은지 (충북대학교 소프트웨어학과) ;
  • 정민성 (충북대학교 소프트웨어학과) ;
  • 반효경 (이화여자대학교 컴퓨터공학과)
  • Received : 2016.06.11
  • Accepted : 2016.08.05
  • Published : 2016.08.31

Abstract

Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

Acknowledgement

Supported by : 한국연구재단

References

  1. https://en.wikipedia.org/wiki/3D_XPoint
  2. E. Lee, S. Yoo, H. Bahn, "Performance Evaluation and Analysis of NVM Storage for Ultra-Light Internet of Things," The Journal of The Institute of Internet, Broadcasting and Communication(JIIBC), Vol. 15, No. 6, pp. 181-186, 2015
  3. Y. Lu, J. Shu, and W. Zheng, "Extending the Lifetime of Flash-based Storage through Reducing Write Amplification from File Systems," Proceedings of the 11th USENIX Conference on File and Storage Technologies (FAST), pp. 73-80, 2013.
  4. P. Desnoyers, "Analytic modeling of SSD write performance," Proceedings of the 5th ACM International Systems and Storage Conference (SYSTOR), 2012.
  5. M. Yang, Y. Chang, C. Tsao, and P. Huang, "New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices," Proceedings of the 50th Annual Design Automation Conference (DAC), 2013.
  6. D. Apalkov, A. Khvalkovskiy, S. Watts, V. Nikitin, X. Tang, D. Lottis, K. Moon, X. Luo, E. Chen, A. Ong, A. Driskill-Smith, and M. Krounbi, "Spin-transfer torque magnetic random access memory (STT-MRAM)," ACM Journal on Emerging Technologies in Computing Systems, 9(2), 2013.
  7. O. Zilberberg, S. Weiss, and S. Toledo, "Phase-change memory: An architectural perspective," ACM Computing Surveys, 45(3), 2013.
  8. Y. Li and K. N. Quader, "NAND Flash memory: challenges and opportunities," Computer, pp. 23-29, 2013.
  9. N. Agrawal, V. Prabhakaran, T. Wobber, J. Davis, M. Manasse, and R. Panigrahy, "Design tradeoffs for SSD performance," Proc. USENIX ATC, pp. 57-70, 2008.
  10. JEDEC, Master trace for 128 GB SSD, http://www.jedec.org/standards-documents/docs/jesd219a_mt.
  11. UMASS trace repository, http://traces.cs.umass.edu.
  12. F. Shu, "Data set management commands proposal for ATA8-ACS2," T13 Technical Committee, United States: At Attachment:e07154r1, 2007.
  13. A. Huffman, "NVM Express: Going Mainstream and What's Next", Intel Developers Forum, 2014.