- Volume 16 Issue 10
DOI QR Code
Efficient Policy for ECC Parity Storing of NAND Flash Memory
낸드플래시 메모리의 효율적인 ECC 패리티 저장 방법
- Received : 2016.08.11
- Accepted : 2016.09.29
- Published : 2016.10.28
This paper presents a new method of parity storing for ECC(error correcting code) in SSD (solid-state drive) and suitable structure of the controller. In general usage of NAND flash memory, we partition a page into data and spare area. ECC parity is stored in the spare area. The method has overhead on area and timing due to access of the page memory discontinuously. This paper proposes a new parity policy storing method that reduces overhead and R(read)/W(write) timing by using whole page area continuously without partitioning. We analyzed overhead and R/W timing. As a result, the proposed parity storing has 13.6% less read access time than the conventional parity policy with 16KB page size. For 4GB video file transfer, it has about a minute less than the conventional parity policy. It will enhance the system performance because the read operation is key function in SSD.
SSD Controller;ECC;Parity Policy
Supported by : 충북대학교
- D. Kim, K. Bang, S. H. Ha, S. W. Chung, and E. Y. Chung, "A Transaction Level Simulator for Performance Analysis of Solid-State Disk(SSD) in PC Environment," Journal of The Institute of Electronics Engineers of Korea, Vol.45, No.12, pp.57-64, 2008.
- C. Sun, T. O. Iwasaki, T. Onagi, K. Johguchi, and K. Takeuchi, "Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD," IEEE Trans.action on Circuits and Systems-I: Regular Papers, Vol.61, No.8, 2014(8).
- Y. Kim, B. Tauras, A. Gupta, and B. Urgaonkar, "FlashSim: A Simulator for NAND Flash-based Solid-State Drives," 2009 First International Conference on Advances in System Simulation, Porto, Portugal, pp.125-131, 2009(9).
- L. Zuolo, C. Zambelli, R. Micheloni, S. Galfano, M. Indaco, S. Di Carlo, P. Prinetto, P. Olivo, and D. Bertozzi, "SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine- Grained Design Space Exploration of Solid State Drives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol.34, No.10, pp.1627-1638, 2015. https://doi.org/10.1109/TCAD.2015.2422834
- S. Gregori, A. Cabrini, 0. Khouri, and G. Torelli, "On-chip error correction techniques for new-generation flash memories," Proc. of IEEE, Vol.91, No.4, pp.602-616, 2003(4).
- W. Liu, J. Rho, and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND fash memories," IEEE Workshop on Signal Processing Systems (SIPS), pp.248-253, 2006.