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Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation

  • Chang, Woojin (Information & Communications Core Technology Research Laboratory, ETRI) ;
  • Park, Young-Rak (Information & Communications Core Technology Research Laboratory, ETRI) ;
  • Mun, Jae Kyoung (Information & Communications Core Technology Research Laboratory, ETRI) ;
  • Ko, Sang Choon (Information & Communications Core Technology Research Laboratory, ETRI)
  • Received : 2015.07.28
  • Accepted : 2015.12.30
  • Published : 2016.02.01

Abstract

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

Acknowledgement

Grant : Next Generation Optical and Electrical Module Technology for Smart Data Center, Development of High Efficiency GaN-Based Key Components and Modules for Base and Mobile Stations, High Efficiency GaN-Based Inverter Using GaN-SBD and FET Discrete Devices Technology

Supported by : Korea Ministry of Science, ICT and Future Planning

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