- Volume 18 Issue 4
DOI QR Code
Design of an FPGA-Based RTL-Level CAN IP Using Functional Simulation for FCC of a Small UAV System
- Choe, Won Seop (Pusan National University) ;
- Han, Dong In (Pusan National University) ;
- Min, Chan Oh (Pusan National University) ;
- Kim, Sang Man (Pusan National University) ;
- Kim, Young Sik (Pusan National University) ;
- Lee, Dae Woo (Pusan National University) ;
- Lee, Ha-Joon (Agency for Defense Development)
- Received : 2017.08.14
- Accepted : 2017.12.11
- Published : 2017.12.30
In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.
Supported by : Pusan National University
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