Enhancing the Accuracy for the Open-loop Resolver to Digital Converters

  • Received : 2017.04.10
  • Accepted : 2017.08.23
  • Published : 2018.01.01


In this study, improvements for error correction, speed, position, and rotation calculation algorithms have been proposed to be used in resolver to digital conversion (RDC) systems. The proposed open-loop system drives the resolver and uses the output signals of the resolver signal to estimate the real time position, the instant speed, and the rotation count with high resolution and accuracy even at high speeds and noise. The proposed solution implements strong features of both closed and open loop based systems while eliminating their weak points. The improvements proposed is resistant to noise owing to digital FIR filter and data averaging techniques. The implementation used for proof of concept is implemented on a hardware using an FPGA and configurable to be used by any resolver.

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Fig. 1. Cross-section of a resolver [23]

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Fig. 2. Resolver signals [22]

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Fig. 3. Block diagram of the general RDC system

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Fig. 4. Block diagram of the proposed RDC system

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Fig. 5. Block diagram of the proposed FPGA design

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Fig. 6. FIR filter magnitude response

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Fig. 7. Position error with and without the FIR filter for aconstant motor

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Fig. 8. Position error with and without data validation

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Fig. 9. Error with and without data averaging for astationary motor at π/8

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Fig. 10. Speed (rad/38μs) for a 10000 rpm rotating motor

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Fig. 11. Data control, rotation sense and position estimatorblock algorithm

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Fig. 12. Position error for a 70Hz ±π sine position input atthe CORDIC and the system output

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Fig. 13. Position error for a 10000 rpm rotating motor atthe CORDIC and the system output

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Fig. 14. Position input, estimated position output androtation count for a motor rotating at 20000 rpm

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Fig. 15. Simulation block diagram

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Fig. 16. The resolver mathematical model

Table 1. Speed calculation errors for different speeds

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Table 2. Properties of the proposed method

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