DOI QR코드

DOI QR Code

Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

  • Sivakumar, M. (Dept. of Electronics and Communication Engineering, SCSVMV) ;
  • Omkumar, S. (Dept. of Electronics and Communication Engineering, SCSVMV)
  • Received : 2018.01.05
  • Accepted : 2018.05.30
  • Published : 2018.11.01

Abstract

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

References

  1. M. Schellmann et al., "FBMC-based air interface for 5G Mobile: Challenges and proposed solutions," in Proc. Int. Conf. Cognitive Radio Oriented Wireless Networks (Crowncom), Oulu, Finland, June 2014.
  2. S. Rajaram and R. Gayathre, "FPGA Implementation of Digital Modulation Schemes," International Journal of Innovative Research in Science, Engineering and Technology, vol.3, Special Issue 3, March 2014.
  3. Faiza Quadri and Aruna D., "FPGA Implementation of Digital Modulation Techniques," International conference on Communication and Signal Processing, IEEE, April 2013.
  4. Akanksha Sinha and Piyush Lotia, "A Study on FPGA Based Digital Modulators," International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 4, no. 4, April 2015.
  5. H. Shousheng and M. Torkelson, "A new approach to pipeline FFT processor," in Proc. Int. Parallel Process. Symp. (IPPS), Apr. 1996, pp. 766-770.
  6. Y.N. Chang et al., "An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design," in IEEE Trans. Circuits Syst. II, vol. 55, no. 12, pp. 1234-1238, Dec 2008. https://doi.org/10.1109/TCSII.2008.2008074
  7. Kai-Jiun Yang, Shang-Ho Tsai and Gene C. H. Chuang, "MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems," IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 21, no. 4, April 2013.
  8. Mario Garrido, J. Grajal, M. A. Sanchez and Oscar Gustafsson, "Pipelined Radix-2K Feed forward FFT Architectures," IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 21, no. 1, January 2013.
  9. N. Kirubananda sarathy and K. Karthikeyan, "Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA," Telecommun Syst, Springer publication, Jan 2016.
  10. H. Lin, M. Gharba, and P. Siohan, "Impact of time and carrier frequency offsets on the FBMC/OQAM modulation scheme," IEEE Trans. Signal Process. vol. 102, pp. 151-162, Sept 2014.
  11. P. Siohan, Siclet, C., and N. Lacaille, "Analysis and design of OFDM/OQAM systems based on filter bank theory," IEEE Trans. Signal Process. , vol. 50, pp. 1170-1183, May 2002. https://doi.org/10.1109/78.995073
  12. M.Caus and A. Perez-Neira, "Transmitter-receiver designs for highly frequency selective channels in MIMO FBMC systems," IEEE Trans. Signal Process. , vol. 60, pp. 6519-6532, Dec. 2012. https://doi.org/10.1109/TSP.2012.2217133
  13. M.Ramesha and T. Venkata Ramana, "A Novel Architecture of FBMC Transmitter using Poly phase Filtering and its FPGA Implementation," Indian Journal of Science and Technology, Vol 9(48), Dec 2016.
  14. Xavier Mestre and David Gregoratti, "Parallelized Structures for MIMO FBMC under Strong Channel Frequency Selectivity," IEEE Transactions on Signal Processing, vol. 64, no. 5, March 1, 2016.
  15. Jeremy Nadal, Charbel Abde and Amer Baghdadi, "Low-complexity pipelined architecture for FBMC/OQAM transmitter," IEEE Transactions on Circuits and Systems-II, vol. 63, no. 1, pp. 1549-7747, Jan 2015.
  16. Doron Gluzer and Shmuel Wimer, "Probability Driven Multi-bit Flip-Flop Integration With Clock Gating," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, March 2017.
  17. Padmini G.Kaushik et al, "Dynamic Power Reduction of Digital Circuits by Clock Gating," International Journal of Advancements in Technology, vol. 4, no. 1, March 2013.
  18. Jiatao Ding et al, "A New Paradigm of Common Sub-expression Elimination by Unification of Addition and Subtraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 10, Oct. 2016.
  19. M. Sivakumar and S. Omkumar, "Integration of Optimized GDI Logic based NOR Gate and Half Adder into PASTA for Low Power & Low Area Applications," International Journal of Applied Engineering Research, vol. 11, no. 4, 2016.
  20. Mohammed Ziaur Rahman et al, "Recursive Approach to the Design of a Parallel Self-Timed Adder," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.1, Jan 2015.