DOI QR코드

DOI QR Code

Demand-based FTL Cache Partitioning for Large Capacity SSDs

대용량 SSD를 위한 요구 기반 FTL 캐시 분리 기법

  • Received : 2019.02.24
  • Accepted : 2019.04.03
  • Published : 2019.04.30

Abstract

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

OBDDBE_2019_v14n2_71_f0001.png 이미지

그림 1. 요구 기반 FTL 읽기 응답시간 분석 Fig. 1 DFTL read latency analysis

OBDDBE_2019_v14n2_71_f0002.png 이미지

그림 2. 요구 기반 FTL의 두 가지 캐시 형태 (a) 엔트리 단위 저장 방식, (b) 페이지 단위 저장 방식 Fig. 2 Two types of mapping cache on DFTL (a) Fine-grained mapping cache, (b) Coarse-grained mapping cache

OBDDBE_2019_v14n2_71_f0003.png 이미지

그림 3. DFTL 캐시 분리 기법의 구조 Fig. 3 DFTL cache partitioning architecture

OBDDBE_2019_v14n2_71_f0004.png 이미지

그림 4. Batch-update 동작 과정 Fig. 4 Batch-update process

OBDDBE_2019_v14n2_71_f0005.png 이미지

그림 5. 읽기/쓰기 성능 Fig. 5 Read/Write throughput

OBDDBE_2019_v14n2_71_f0006.png 이미지

그림 6. 쓰기 증폭 인자 Fig. 6 Write amplification factor

OBDDBE_2019_v14n2_71_f0007.png 이미지

그림 7. 읽기 응답시간 누적분포 Fig. 7 Read latency CDF

Acknowledgement

Supported by : 한국연구재단

References

  1. Available on : https://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf
  2. Available on : https://www.samsung.com/semiconductor/ssd/enterprise-ssd/
  3. A. Gupta, Y. Kim, B. Urgaonkar, “DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings,” Journal of ACM, Vol. 44, No. 3, pp. 229-240, 2009.
  4. X. Li, J. Du, “Adaptive and Attribute-based Trust Model for Service-level Agreement Guarantee in Cloud Computing,” Journal of IET Information Security, Vol. 7, No. 1, pp. 39-50, 2013. https://doi.org/10.1049/iet-ifs.2012.0232
  5. D. Serrano, S. Bouchenak, Y. Kouki, T. Ledoux, J. Lejeune, J. Sopena, L. Arates, P. Sens, "Towards Qos-oriented Sla Guarantees for Online Cloud Services," Proceedings of 13th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing, pp. 50-57, 2013.
  6. Z. Qin, Y. Wang, D. Liu, Z. Shao, "A Two-level Caching Mechanism for Demand-based Page-level Address Mapping in NAND Flash Memory Storage Systems," Proceedings of 17th IEEE Real-Time and Embedded Technology and Application Symposium, pp. 157-166, 2011.
  7. M. Wang, Y. Zhang, W. Kang, "ZFTL: A Zone-based Flash Translation Layer with a Two-tier Selective Caching Mechanism," Proceedings of 14th IEEE International Conference on Communication Technology, pp. 578-588, 2012.
  8. C. Wang, W. Wong, "TreeFTL: Efficient RAM Management for High Performance of NAND Flash-based Storage Systems," Proceedings of the Conference on Design, Automation and Test in Europe, pp. 374-379, 2013.
  9. S. Jiang, L. Zhang, X. Yuan, H. Hu, Y. Chen, "S-FTL: An Efficient Address Translation for Flash Memory by Exploiting Spatial Locality," Proceedings of 27th IEEE Symposium on Mass Storage Systems and Technologies, pp. 1-12, 2011.
  10. H.B. Kim, J.W. Bae, J.S. Im, S.J. Lee, "Address Translation with Bounded Tail Latency for Large Capacity SSDs," Proceedings of Korea Software Congress (KSC), pp. 1481-1483, 2018 (in Korean).