Design and implementation of an improved MA-APUF with higher uniqueness and security

  • Li, Bing (School of Microelectronics, School of Cyber Science and Engineering, SEU-FiberHome Joint Research Center, Southeast University) ;
  • Chen, Shuai (School of Microelectronics, School of Cyber Science and Engineering, SEU-FiberHome Joint Research Center, Southeast University) ;
  • Dan, Fukui (School of Microelectronics, School of Cyber Science and Engineering, SEU-FiberHome Joint Research Center, Southeast University)
  • Received : 2019.02.20
  • Accepted : 2019.08.28
  • Published : 2020.04.03


An arbiter physical unclonable function (APUF) has exponential challenge-response pairs and is easy to implement on field-programmable gate arrays (FPGAs). However, modeling attacks based on machine learning have become a serious threat to APUFs. Although the modeling-attack resistance of an MA-APUF has been improved considerably by architecture modifications, the response generation method of an MA-APUF results in low uniqueness. In this study, we demonstrate three design problems regarding the low uniqueness that APUF-based strong PUFs may exhibit, and we present several foundational principles to improve the uniqueness of APUF-based strong PUFs. In particular, an improved MA-APUF design is implemented in an FPGA and evaluated using a well-established experimental setup. Two types of evaluation metrics are used for evaluation and comparison. Furthermore, evolution strategies, logistic regression, and K-junta functions are used to evaluate the security of our design. The experiment results reveal that the uniqueness of our improved MA-APUF is 81.29% (compared with that of the MA-APUF, 13.12%), and the prediction rate is approximately 56% (compared with that of the MA-APUF (60%-80%).


Supported by : Shenzhen Science, Technology and Innovation Commission (SZSTI), National Natural Science Foundation of China (NSFC), Southeast University


  1. R. Pappu et al., Physical one-way functions, Sci. 297 (2002), no. 5589, 2026-2030.
  2. L. Bing and C. Shuai, A dynamic PUF anti-aging authentication system based on restrict race code, Sci. China Inf. Sci. 59 (2016), no. 1, 12108-012108.
  3. S. Chen and B. Li, A dynamic reseeding DRBG based on SRAM PUFs, in Proc. Int. Conf. Cyber-Enabled Distrib. Comput. Knowl. Discov., Chengdu, China, Feb. 2017, pp. 50-53.
  4. J. Delvaux et al., Helper data algorithms for puf-based key generation: Overview and analysis, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2015), no. 6, 889-902.
  5. R. Maes and I. Verbauwhede, Physically unclonable functions: A study on the state of the art and future research directions, in Towards Hardware-intrinsic Security, Springer, Heidelberg, New York, 2010, pp. 3-37.
  6. R. Ulrich et al., Modeling attacks on physical unclonable functions, in Proc. ACM Conf. Comput. Commun. Security, Chicago, IL, USA, 2010, pp. 237-249.
  7. J. Guajardo et al., FPGA intrinsic PUFs and their use for IP protection, in Int. Workshop Cryptograph. Hardw. Embed. Syst., Vienna, Austria, 2007, pp. 63-80.
  8. S. S. Kumar et al., Extended abstract: The butterfly PUF protecting IP on every FPGA, in Proc. IEEE Int, Workshop hardw.-Oriented Security Trust Anaheim, CA, 2008, pp. 67-70.
  9. A. Maiti and P. Schaumont, Improving the quality of a physical unclonable function using configurable ring oscillators, in Proc. Int. Conf. Field Prog. Logic Appl., Prague, Czech Republic, 2009, pp. 703-707.
  10. B. Gassend et al., Silicon physical random functions, in Proc. ACM Conf. Comput. Commun. Security, Washington, D.C., USA, 2002, pp. 148-160.
  11. G. E. Suh and S. Devadas, Physical unclonable functions for device authentication and secret key generation, in Proc. ACM/IEEE Des. Autom. Conf., San Diego, CA, USA, 2007, pp. 9-14.
  12. L. Yingjie and K. K. Parhi, Reconfigurable architectures for silicon physical unclonable functions, in Proc. IEEE Int. Conf. Electro/ Inform. Technol., Mankato, MN, USA, 2011, pp. 1-7.
  13. M. Mehrdad, F. Koushanfar, and M. Potkonjak, Techniques for design and implementation of secure reconfigurable PUFs, ACM Trans. Reconfig. Tech. Syst. 2 (2009), no. 1, 1-33.
  14. R. Maes, P. Tuyls, and I. Verbauwhede, A soft decision helper data algorithm for SRAM PUFs, in Proc. IEEE Int. Conf. Symp. Inf. Theory, Seoul, Rep. of Korea, 2009, pp. 2101-2105.
  15. A. Vijayakumar and S. Kundu, A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics, in Proc. Des. Autom. Test Europe Conf. Exhibit., Grenoble, France, 2015, pp. 653-658.
  16. D. P. Sahoo et al., A case of lightweight PUF constructions: Cryptanalysis and machine learning attacks, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2015), no. 8, 1334-1343.
  17. U. Ruhrmair et al., PUF modeling attacks on simulated and silicon data, IEEE Trans. Inf. Forensics Secur. 8 (2013), no. 11, 1876-1891.
  18. P. H. Nguyen and D. P. Sahoo, Lightweight and secure PUFs: A survey (invited paper), in Proc. Int. Conf. Sec., Pune, India, 2014, pp. 1-13.
  19. U. Ruhrmair, Power and timing side channels for PUFs and their efficient exploitation, in Proc. Cryptographic Hardw. Embedded Syst., Busan, Rep. of Korea, 2013, pp. 476-492.
  20. R. Kumar and W. Burleson, Side-channel assisted modeling attacks on feed-forward arbiter PUFs using silicon data, in Proc. Int. Workshop Radio Freq. Ident. Sec. Privacy Issues, New York, NY, USA, 2015, pp. 53-67.
  21. A. Mahmoud et al., Combined modeling and side channel attacks on strong PUFs, Cryptology ePrintArchive, Report2013/632, 2013.
  22. A. Vijayakumar et al., Machine learning resistant strong PUF: Possible or a pipe dream? in Proc. IEEE Int. Symp. Hardw. Orient. Sec. Trust, McLean, VA, USA, 2016, pp. 19-24.
  23. R. Kumar and W. Burleson, On design of a highly secure PUF based on non-linear current mirrors, in Proc. IEEE Int. Symp. Hardw. Orient. Sec. Trust, Arlington, VA, USA, 2014, pp. 38-43.
  24. M. Takanori et al., A new arbiter PUF for enhancing unpredictability on FPGA, Sci. World J. 2015 (2015), 1-13.
  25. J. Ye, Y. Hu, and X. Li, RPUF: Physical unclonable function with randomized challenge to resist modeling attack, in Proc. IEEE Asian Hardw. Orient. Sec. Trust, Wilan, Taiwan, 2016, pp. 1-6.
  26. G. Yansong et al., Obfuscated challenge-response: A secure lightweight authentication mechanism for PUF-based pervasive devices, in Proc. IEEE Int. Conf. Pervas. Comput. Commun. Workshops, Sydney, Australia, 2016, pp. 1-6.
  27. M. Rostami et al., Robust and reverse-engineering resilient PUF authentication and key-exchange by substring matching, IEEE Trans. Emerg. Topics Comput. 2 (2014), no. 1, 37-49.
  28. M. Yoshikawa and A. Naruse, Multiplexing aware arbiter physical unclonable function, in Proc. IEEE Int. Conf. Inf. Reuse Integr., Las Vegas, NV, USA, 2012, pp. 639-644.
  29. M. Majzoobi et al., Automated design, implementation, and evaluation of arbiter-based PUF on FPGA using programmable delay lines, Cryptology ePrint Archive, Report 2014/639, 2014,
  30. A. Maiti, V. Gunreddy, P. Schaumont, A systematic method to evaluate and compare the performance of physical unclonable functions, Springer, New York, 2013.
  31. F. Ganji et al., Having no mathematical model may not secure PUFs, J. Cryptogr. Eng. 7 (2017), no. 4, 1-16.
  32. Y. Hori et al., Quantitative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs, in Proc. Int. Conf. Reconf. Comput. FPGAs, Quintana Roo, Mexico, 2011, pp. 298-303.
  33. G. Yansong, Modeling attack resilient reconfigurable latent obfuscation technique for PUF based lightweight authentication (2017).
  34. D. Lim et al., Extracting secret keys from integrated circuits, IEEE Trans. Very Large Scale Integ. Syst. 13 (2005), no. 10, 1200-1205.