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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of Computing Science and Engineering
Journal Basic Information
Journal DOI :
Korean Institute of Information Scientists and Engineers
Editor in Chief :
In-Sup Lee / Il-Yeol Song / Jong C. Park / Tae-Whan Kim
Volume & Issues
Volume 6, Issue 4 - Dec 2012
Volume 6, Issue 3 - Sep 2012
Volume 6, Issue 2 - Jun 2012
Volume 6, Issue 1 - Mar 2012
Selecting the target year
Design and Implementation of a Framework for Context-Aware Preference Queries
Roocks, Patrick ; Endres, Markus ; Huhn, Alfons ; KieBling, Werner ; Mandl, Stefan ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 243~256
DOI : 10.5626/JCSE.2012.6.4.243
In this paper we present a framework for a novel kind of context-aware preference query composition whereby queries for the Preference SQL system are created. We choose a commercial e-business platform for outdoor activities as a use case and develop a context model for this domain within our framework. The suggested model considers explicit user input, domain-specific knowledge, contextual knowledge and location-based sensor data in a comprehensive approach. Aside from the theoretical background of preferences, the optimization of preference queries and our novel generator based model we give special attention to the aspects of the implementation and the practical experiences. We provide a sketch of the implementation and summarize our user studies which have been done in a joint project with an industrial partner.
Design Methodologies for Reliable Clock Networks
Joo, Deokjin ; Kang, Minseok ; Kim, Taewhan ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 257~266
DOI : 10.5626/JCSE.2012.6.4.257
This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.
Static Timing Analysis of Shared Caches for Multicore Processors
Zhang, Wei ; Yan, Jun ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 267~278
DOI : 10.5626/JCSE.2012.6.4.267
The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).
High Performance Computing: Infrastructure, Application, and Operation
Park, Byung-Hoon ; Kim, Youngjae ; Kim, Byoung-Do ; Hong, Taeyoung ; Kim, Sungjun ; Lee, John K. ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 280~286
DOI : 10.5626/JCSE.2012.6.4.280
The last decades have witnessed an increasingly indispensible role of high performance computing (HPC) in science, business and financial sectors, as well as military and national security areas. To introduce key aspects of HPC to a broader community, an HPC session was organized for the first time ever for the United States and Korea Conference (UKC) during 2012. This paper summarizes four invited talks that each covers scientific HPC applications, large-scale parallel file systems, administration/maintenance of supercomputers, and green technology towards building power efficient supercomputers of the next generation.
A Comparative Performance Study for Compute Node Sharing
Park, Jeho ; Lam, Shui F. ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 287~293
DOI : 10.5626/JCSE.2012.6.4.287
We introduce a methodology for the study of the application-level performance of time-sharing parallel jobs on a set of compute nodes in high performance clusters and report our findings. We assume that parallel jobs arriving at a cluster need to share a set of nodes with the jobs of other users, in that they must compete for processor time in a time-sharing manner and other limited resources such as memory and I/O in a space-sharing manner. Under the assumption, we developed a methodology to simulate job arrivals to a set of compute nodes, and gather and process performance data to calculate the percentage slowdown of parallel jobs. Our goal through this study is to identify a better combination of jobs that minimize performance degradations due to resource sharing and contention. Through our experiments, we found a couple of interesting behaviors for overlapped parallel jobs, which may be used to suggest alternative job allocation schemes aiming to reduce slowdowns that will inevitably result due to resource sharing on a high performance computing cluster. We suggest three job allocation strategies based on our empirical results and propose further studies of the results using a supercomputing facility at the San Diego Supercomputing Center.
Computational Methods for On-Node Performance Optimization and Inter-Node Scalability of HPC Applications
Kim, Byoung-Do ; Rosales-Fernandez, Carlos ; Kim, Sungho ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 294~309
DOI : 10.5626/JCSE.2012.6.4.294
In the age of multi-core and specialized accelerators in high performance computing (HPC) systems, it is critical to understand application characteristics and apply suitable optimizations in order to fully utilize advanced computing system. Often time, the process involves multiple stages of application performance diagnosis and a trial-and-error type of approach for optimization. In this study, a general guideline of performance optimization has been demonstrated with two class-representing applications. The main focuses are on node-level optimization and inter-node scalability improvement. While the number of optimization case studies is somewhat limited in this paper, the result provides insights into the systematic approach in HPC applications performance engineering.
Algorithm for Improving the Computing Power of Next Generation Wireless Receivers
Rizvi, Syed S. ;
Journal of Computing Science and Engineering, volume 6, issue 4, 2012, Pages 310~319
DOI : 10.5626/JCSE.2012.6.4.310
Next generation wireless receivers demand low computational complexity algorithms with high computing power in order to perform fast signal detections and error estimations. Several signal detection and estimation algorithms have been proposed for next generation wireless receivers which are primarily designed to provide reasonable performance in terms of signal to noise ratio (SNR) and bit error rate (BER). However, none of them have been chosen for direct implementation as they offer high computational complexity with relatively lower computing power. This paper presents a low-complexity power-efficient algorithm that improves the computing power and provides relatively faster signal detection for next generation wireless multiuser receivers. Measurement results of the proposed algorithm are provided and the overall system performance is indicated by BER and the computational complexity. Finally, in order to verify the low-complexity of the proposed algorithm we also present a formal mathematical proof.