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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 1, Issue 4 - Dec 2001
Volume 1, Issue 3 - Sep 2001
Volume 1, Issue 2 - Jun 2001
Volume 1, Issue 1 - Mar 2001
Selecting the target year
Current Status and Prospects of FET-type Ferroelectric Memories
Ishiwara, Hiroshi ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 1~14
Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.
A Technique for Analyzing LSI Failures Using Wafer-level Emission Analysis System
Higuchi, Yasuhisa ; Kawaguchi, Yasumasa ; Sakazume, Tatsumi ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 15~19
Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.
A SDR/DDR 4Gb DRAM with
Kim, Ki-Nam ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 20~30
4Gb DRAM having
cell size has been successfully developed using 0.11
DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes
DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.
W Polymetal Gate Technology for Giga Bit DRAM
Jung, Jong-Wan ; Han, Sang-Beom ; Lee, Kyungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 31~39
W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail.
adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional
/Poly-silicon gate process. These results undoubtedly show that
is the strongest candidate as a word line for Giga bit DRAM.
Characteristics of Si Nano-Crystal Memory
Kwangseok Han ; Kim, Ilgweon ; Hyungcheol Shin ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 40~49
We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at
for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of
. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of
, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.
High-Speed Signaling in SDARM Bus Interface Channels : Review
Park, Hong-June ; Sohn, Young-Soo ; Park, Jin-Seok ; Bae, Seung-Jun ; Park, Seok-Woo ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 50~69
Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.
RF MEMS Devices for Wireless Applications
Park, Jae Y. ; Jong U. Bu ; Lee, Joong W. ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 70~83
In this paper, the recent progress of RF MEMS research for wireless/mobile communications is reviewed. The RF MEMS components reviewed in this paper include RF MEMS switches, tunable capacitors, high Q inductors, and thin film bulk acoustic resonators (TFBARs) to become core components for constructing miniaturized on chip RF transceiver with multi-band and multi-mode operation. Specific applications are also discussed for each of these components with emphasis on for miniaturization, integration, and performance enhancement of existing and future wireless transceiver developments.
Electromagnetic Micro x-y Stage for Probe-Based Data Storage
Park, Jae-joon ; Park, Hongsik ; Kim, Kyu-Yong ; Jeon, Jong-Up ;
JSTS:Journal of Semiconductor Technology and Science, volume 1, issue 1, 2001, Pages 84~93
An electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield
in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio (
in width and
in depth). Silicon flexures with a height of
were fabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was
and the maximum displacement was
at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reverse-tapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.