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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 10, Issue 4 - Dec 2010
Volume 10, Issue 3 - Sep 2010
Volume 10, Issue 2 - Jun 2010
Volume 10, Issue 1 - Mar 2010
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Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
Anuar, Nazrul ; Takahashi, Yasuhiro ; Sekine, Toshikazu ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 1~10
DOI : 10.5573/JSTS.2010.10.1.001
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to
. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
A New Approach for Accurate RTL Power Macro-Modeling
Kawauchi, Hirofumi ; Taniguchi, Ittetsu ; Fukui, Masahiro ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 11~19
DOI : 10.5573/JSTS.2010.10.1.011
Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.
Mosfet Models, Quantum Mechanical Effects and Modeling Approaches: A Review
Chaudhry, Amit ; Roy, J.N. ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 20~27
DOI : 10.5573/JSTS.2010.10.1.020
Modeling is essential to simulate the operation of integrated circuit (IC) before its fabrication. Seeing a large number of Metal-Oxide-Silicon Field-Effect-Transistor (MOSFET) models available, it has become important to understand them and compare them for their pros and cons. The task becomes equally difficult when the complexity of these models becomes very high. The paper reviews the mainstream models with their physical relevance and their comparisons. Major short-channel and quantum effects in the models are outlined. Emphasis is set upon the latest compact models like BSIM, MOS Models 9/11, EKV, SP etc.
Multiple Network-on-Chip Model for High Performance Neural Network
Dong, Yiping ; Li, Ce ; Lin, Zhen ; Watanabe, Takahiro ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 28~36
DOI : 10.5573/JSTS.2010.10.1.028
Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.
A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC
Hirai, Naoyuki ; Song, Tian ; Liu, Yizhong ; Shimamoto, Takashi ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 37~44
DOI : 10.5573/JSTS.2010.10.1.037
New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.
Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface
Lee, Jang-Woo ; Kim, Hong-Jung ; Nam, Young-Jin ; Yoo, Chang-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 45~48
DOI : 10.5573/JSTS.2010.10.1.045
An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.
Fast Circuit Simulation Based on Parallel-Distributed LIM using Cloud Computing System
Inoue, Yuta ; Sekine, Tadatoshi ; Hasegawa, Takahiro ; Asai, Hideki ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 49~54
DOI : 10.5573/JSTS.2010.10.1.049
This paper describes a fast circuit simulation technique using the latency insertion method (LIM) with a parallel and distributed leapfrog algorithm. The numerical simulation results on the PC cluster system that uses the cloud computing system are shown. As a result, it is confirmed that our method is very useful and practical.
Level Up/Down Converter with Single Power-Supply Voltage for Multi-VDD Systems
An, Ji-Yeon ; Park, Hyoun-Soo ; Kim, Young-Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 55~60
DOI : 10.5573/JSTS.2010.10.1.055
For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.
Analytic Threshold Voltage Model of Recessed Channel MOSFETs
Kwon, Yong-Min ; Kang, Yeon-Sung ; Lee, Sang-Hoon ; Park, Byung-Gook ; Shin, Hyung-Cheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 61~65
DOI : 10.5573/JSTS.2010.10.1.061
Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.
Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications
Gupta, Ritesh ; Kaur, Ravneet ; Aggarwal, Sandeep Kr ; Gupta, Mridula ; Gupta, R.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 1, 2010, Pages 66~77
DOI : 10.5573/JSTS.2010.10.1.066
Improvement in breakdown voltage (
) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length (
), but due to lithographic limitation, shortening
below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the
of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in
can be obtained by applying field plates, especially at the drain side. The important parameters affecting
and cut-off frequency (
) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate,
-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.