Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 10, Issue 4 - Dec 2010
Volume 10, Issue 3 - Sep 2010
Volume 10, Issue 2 - Jun 2010
Volume 10, Issue 1 - Mar 2010
Selecting the target year
Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs
Ishihara, Shota ; Xia, Zhengfan ; Hariyama, Masanori ; Kameyama, Michitaka ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 165~175
DOI : 10.5573/JSTS.2010.10.3.165
This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.
Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS
Sekiguchi, Takayuki ; Amakawa, Shuhei ; Ishihara, Noboru ; Masu, Kazuya ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 176~184
DOI : 10.5573/JSTS.2010.10.3.176
A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is
. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is
. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low
. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.
VLSI Implementation of Auto-Correlation Architecture for Synchronization of MIMO-OFDM WLAN Systems
Cho, Jong-Min ; Kim, Jin-Sang ; Cho, Won-Kyung ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 185~192
DOI : 10.5573/JSTS.2010.10.3.185
This paper presents a hardware-efficient auto-correlation scheme for the synchronization of MIMO-OFDM based wireless local area network (WLAN) systems, such as IEEE 802.11n. Carrier frequency offset (CFO) estimation for the frequency synchronization requires high complexity auto-correlation operations of many training symbols. In order to reduce the hardware complexity of the MIMO-OFDM synchronization, we propose an efficient correlation scheme based on time-multiplexing technique and the use of reduced samples while preserving the performance. Compared to a conventional architecture, the proposed architecture requires only 27% logic gates and 22% power consumption with acceptable BER performance loss.
High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture
Park, Jeong-In ; Lee, Ki-Hoon ; Choi, Chang-Seok ; Lee, Han-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 193~202
DOI : 10.5573/JSTS.2010.10.3.193
This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.
An Analytical Model of the First Eigen Energy Level for MOSFETs Having Ultrathin Gate Oxides
Yadav, B. Pavan Kumar ; Dutta, Aloke K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 203~212
DOI : 10.5573/JSTS.2010.10.3.203
In this paper, we present an analytical model for the first eigen energy level (
) of the carriers in the inversion layer in present generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. Commonly used approaches to evaluate
make either or both of the following two assumptions: one is that the barrier height at the oxide-semiconductor interface is infinite (with the consequence that the wave function at this interface is forced to zero), while the other is the triangular potential well approximation within the semiconductor (resulting in a constant electric field throughout the semiconductor, equal to the surface electric field). Obviously, both these assumptions are wrong, however, in order to correctly account for these two effects, one needs to solve Schrodinger and Poisson equations simultaneously, with the approach turning numerical and computationally intensive. In this work, we have derived a closed-form analytical expression for
, with due considerations for both the assumptions mentioned above. In order to account for the finite barrier height at the oxide-semiconductor interface, we have used the asymptotic approximations of the Airy function integrals to find the wave functions at the oxide and the semiconductor. Then, by applying the boundary condition at the oxide-semiconductor interface, we developed the model for
. With regard to the second assumption, we proposed the inclusion of a fitting parameter in the wellknown effective electric field model. The results matched very well with those obtained from Li's model. Another unique contribution of this work is to explicitly account for the finite oxide-semiconductor barrier height, which none of the reported works considered.
Optically Controlled Silicon MESFET Fabrication and Characterizations for Optical Modulator/Demodulator
Chattopadhyay, S.N. ; Overton, C.B. ; Vetter, S. ; Azadeh, M. ; Olson, B.H. ; Naga, N. El ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 213~224
DOI : 10.5573/JSTS.2010.10.3.213
An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 nm wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.
Investigation of Thermal Noise Factor in Nanoscale MOSFETs
Jeon, Jong-Wook ; Park, Byung-Gook ; Shin, Hyung-Cheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 225~231
DOI : 10.5573/JSTS.2010.10.3.225
In this paper, we investigate the channel thermal noise in nanoscale MOSFETs. Simple analytical model of thermal noise factor in nanoscale MOSFETs is presented and it is verified with accurately measured noise data. The noise factor is expressed in terms of the channel conductance and the electric field in the gradual channel region. The proposed noise model can predict the channel thermal noise behavior in all operating bias regions from the long-channel to nanoscale MOSFETs. From the measurement results, we observed that the thermal noise model for the long-channel MOSFETs does not always underestimate the short-channel thermal noise.
A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines
Jung, Hae-Kang ; Lee, Soo-Min ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 232~239
DOI : 10.5573/JSTS.2010.10.3.232
By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a
CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.
Threshold Voltage Control through Layer Doping of Double Gate MOSFETs
Joseph, Saji ; George, James T. ; Mathew, Vincent ;
JSTS:Journal of Semiconductor Technology and Science, volume 10, issue 3, 2010, Pages 240~250
DOI : 10.5573/JSTS.2010.10.3.240
Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.