Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 11, Issue 4 - Dec 2011
Volume 11, Issue 3 - Sep 2011
Volume 11, Issue 2 - Jun 2011
Volume 11, Issue 1 - Mar 2011
Selecting the target year
Real-time In-situ Plasma Etch Process Monitoring for Sensor Based-Advanced Process Control
Ahn, Jong-Hwan ; Gu, Ja-Myong ; Han, Seung-Soo ; Hong, Sang-Jeen ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 1~5
DOI : 10.5573/JSTS.2011.11.1.001
To enter next process control, numerous approaches, including run-to-run (R2R) process control and fault detection and classification (FDC) have been suggested in semiconductor manufacturing industry as a facilitation of advanced process control. This paper introduces a novel type of optical plasma process monitoring system, called plasma eyes chromatic system (PECSTM) and presents its potential for the purpose of fault detection. Qualitatively comparison of optically acquired signal levels vs. process parameter modifications are successfully demonstrated, and we expect that PECSTM signal can be a useful indication of onset of process change in real-time for advanced process control (APC).
Sign-Select Lookahead CORDIC based High-Speed QR Decomposition Architecture for MIMO Receiver Applications
Lee, Min-Woo ; Park, Jong-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 6~14
DOI : 10.5573/JSTS.2011.11.1.006
This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25
CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4
4 matrix decomposition.
Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias
Kim, Hye-Won ; Kim, Dong-Chul ; Eo, Yung-Seon ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 15~22
DOI : 10.5573/JSTS.2011.11.1.015
Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.
A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology
Kim, Bin-Hee ; Yan, Long ; Yoo, Jerald ; Yoo, Hoi-Jun ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 23~32
DOI : 10.5573/JSTS.2011.11.1.023
A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18
1P6M CMOS technology and occupies 1.17
including pads. It dissipates only 1.1
with 1 V supply voltage while operating at 100 kS/s.
Smart Bus Arbiter for QoS control in H.264 decoders
Lee, Chan-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 33~39
DOI : 10.5573/JSTS.2011.11.1.033
H.264 decoders usually have pipeline architecture by a macroblock or a 4
4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.
A Two-Dimensional (2D) Analytical Model for the Potential Distribution and Threshold Voltage of Short-Channel Ion-Implanted GaAs MESFETs under Dark and Illuminated Conditions
Tripathi, Shweta ; Jit, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 40~50
DOI : 10.5573/JSTS.2011.11.1.040
A two-dimensional (2D) analytical model for the potential distribution and threshold voltage of short-channel ion-implanted GaAs MESFETs operating in the sub-threshold regime has been presented. A double-integrable Gaussian-like function has been assumed as the doping distribution profile in the vertical direction of the channel. The Schottky gate has been assumed to be semi-transparent through which optical radiation is coupled into the device. The 2D potential distribution in the channel of the short-channel device has been obtained by solving the 2D Poisson's equation by using suitable boundary conditions. The effects of excess carrier generation due to the incident optical radiation in channel region have been included in the Poisson's equation to study the optical effects on the device. The potential function has been utilized to model the threshold voltage of the device under dark and illuminated conditions. The proposed model has been verified by comparing the theoretically predicted results with simulated data obtained by using the commercially available
2D device simulator.
Fast Generation of Multiple Custom Instructions under Area Constraints
Wu, Di ; Lee, Im-Yong ; Ahn, Jun-Whan ; Choi, Ki-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 51~58
DOI : 10.5573/JSTS.2011.11.1.051
Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.
A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 ㎛ CMOS
Choi, Jae-Yi ; Seo, Shin-Hyouk ; Moon, Hyun-Won ; Nam, Il-Ku ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 59~64
DOI : 10.5573/JSTS.2011.11.1.059
A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13
CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.
Bandpass Filters using T-shape Stepped Impedance Resonators for Wide Harmonics Suppression and their Application for a Diplexer
Lerdwanittip, Reungyot ; Namsang, Apirada ; Akkaraekthalin, Prayoot ;
JSTS:Journal of Semiconductor Technology and Science, volume 11, issue 1, 2011, Pages 65~72
DOI : 10.5573/JSTS.2011.11.1.065
In this paper, the T-shape stepped impedance resonators are adopted for the design of microstrip bandpass filters for wide harmonics suppression. The proposed filters are operated at the center frequency of 2.44 GHz and 5.20 GHz, respectively. These bandpass filters have been also applied for a high performance diplexer. The insertion losses at the center frequencies of 2.44 and 5.20 GHz are 1.23 and 1.18, respectively. The applicable return losses for both frequency bands and a wide stopband better than 17 dB up to 20 GHz have been obtained.