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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 12, Issue 4 - Dec 2012
Volume 12, Issue 3 - Sep 2012
Volume 12, Issue 2 - Jun 2012
Volume 12, Issue 1 - Mar 2012
Selecting the target year
A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic
Jun, Joong-Won ; Kim, Dae-Yun ; Song, Min-Kyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 1~9
DOI : 10.5573/JSTS.2012.12.1.1
A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of
LSB and an INL of
LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is
, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.
A Clock Regenerator using Two 2
Order Sigma-Delta Modulators for Wide Range of Dividing Ratio
Oh, Seung-Wuk ; Kim, Sang-Ho ; Im, Sang-Soon ; Ahn, Yong-Sung ; Kang, Jin-Ku ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 10~17
DOI : 10.5573/JSTS.2012.12.1.10
This paper presents a clock regenerator using two
(sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different
modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18
CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.
Implementation of Single-Wire Communication Protocol for 3D IC Thermal Management Systems using a Thin Film Thermoelectric Cooler
Kim, Nam-Jae ; Lee, Hyun-Ju ; Kim, Shi-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 18~23
DOI : 10.5573/JSTS.2012.12.1.18
We propose and implement a single-wire communication protocol for thermal management systems using thin film thermoelectric modules for 3D IC cooling. The proposed single-wire communication protocol connects the temperature sensors, located near hot spots, to measure the local temperature of the chip. A unique ID number identifying the location of each hot spot is assigned to each temperature sensor. The prototype chip was fabricated by a
CMOS MPW process, and the operation of the chip is verified.
A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX
Shin, Kyung-Wook ; Kim, Hae-Ju ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 24~33
DOI : 10.5573/JSTS.2012.12.1.24
This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a
CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.
Interval Scan Inspection Technique for Contact Failure of Advanced DRAM Process using Electron Beam-Inspection System
Oh, J.H. ; Kwon, G. ; Mun, D.Y. ; Kim, D.J. ; Han, I.K. ; Yoo, H.W. ; Jo, J.C. ; Ominami, Y. ; Ninomiya, T. ; Nozoe, M. ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 34~40
DOI : 10.5573/JSTS.2012.12.1.34
We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.
Fluorine Effects on NMOS Characteristics and DRAM Refresh
Choi, Deuk-Sung ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 41~45
DOI : 10.5573/JSTS.2012.12.1.41
We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.
Avalanche Hot Source Method for Separated Extraction of Parasitic Source and Drain Resistances in Single Metal-Oxide-Semiconductor Field Effect Transistors
Baek, Seok-Cheon ; Bae, Hag-Youl ; Kim, Dae-Hwan ; Kim, Dong-Myong ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 46~52
DOI : 10.5573/JSTS.2012.12.1.46
Separate extraction of source (
) and drain (
) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of
in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of
. We also confirmed that there is a negligible drift in the threshold voltage (
) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.
A "Thru-Short-Open" De-embedding Method for Accurate On-Wafer RF Measurements of Nano-Scale MOSFETs
Kim, Ju-Young ; Choi, Min-Kwon ; Lee, Seong-Hearn ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 53~58
DOI : 10.5573/JSTS.2012.12.1.53
A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.
A Study on the Electrical Characteristic Analysis of c-Si Solar Cell Diodes
Choi, Pyung-Ho ; Kim, Hyo-Jung ; Baek, Do-Hyun ; Choi, Byoung-Deog ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 59~65
DOI : 10.5573/JSTS.2012.12.1.59
A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the device's front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V.
Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET
Patil, Ganesh C. ; Qureshi, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 66~74
DOI : 10.5573/JSTS.2012.12.1.66
In this paper, the impact of segregation layer density (
) and length (
) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the
the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the
the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing
of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.
Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters
Yu, Sang-Dae ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 75~87
DOI : 10.5573/JSTS.2012.12.1.75
A design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition, small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.
Bandwidth - Power Optimization Methodology for SFB Filter Design
Shin, Hun-Do ; Ryu, Seung-Tak ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 88~98
DOI : 10.5573/JSTS.2012.12.1.88
In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18
CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33
, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW - power efficiency.
The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization
Li, Jing ; Ning, Ning ; Du, Ling ; Yu, Qi ; Liu, Yang ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 99~106
DOI : 10.5573/JSTS.2012.12.1.99
For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on
induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.
Bandwidth-Related Optimization in High-Speed Frequency Dividers using SiGe Technology
Nan, Chao-Zhou ; Yu, Xiao-Peng ; Lim, Wei-Meng ; Hu, Bo-Yu ; Lu, Zheng-Hao ; Liu, Yang ; Yeo, Kiat-Seng ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 1, 2012, Pages 107~116
DOI : 10.5573/JSTS.2012.12.1.107
In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.