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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
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Volume & Issues
Volume 12, Issue 4 - Dec 2012
Volume 12, Issue 3 - Sep 2012
Volume 12, Issue 2 - Jun 2012
Volume 12, Issue 1 - Mar 2012
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A Bus Data Compression Method on a Phase-Based On-Chip Bus
Lee, Jae-Sung ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 117~126
DOI : 10.5573/JSTS.2012.12.2.117
This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively
A Real-Time Virtual Re-Convergence Hardware Platform
Kim, Jae-Gon ; Kim, Jong-Hak ; Ham, Hun-Ho ; Kim, Jueng-Hun ; Park, Chan-Oh ; Park, Soon-Suk ; Cho, Jun-Dong ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 127~138
DOI : 10.5573/JSTS.2012.12.2.127
In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.
Post Silicon Management of On-Package Variation Induced 3D Clock Skew
Kim, Tak-Yung ; Kim, Tae-Whan ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 139~149
DOI : 10.5573/JSTS.2012.12.2.139
A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.
An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
Kim, Dong-Kyun ; Jung, Jun-Hee ; Nguyen, Thuy Tuong ; Kim, Dai-Jin ; Kim, Mun-Sang ; Kwon, Key-Ho ; Jeon, Jae-Wook ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 150~161
DOI : 10.5573/JSTS.2012.12.2.150
Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image.
Design of High-Performance Unified Circuit for Linear and Non-Linear SVM Classifications
Kim, Soo-Jin ; Lee, Seon-Young ; Cho, Kyeong-Soon ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 162~167
DOI : 10.5573/JSTS.2012.12.2.162
This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.
High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission
Park, Kwang-Il ; Koo, Ja-Hyuck ; Shin, Won-Hwa ; Jun, Young-Hyun ; Kong, Bai-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 168~174
DOI : 10.5573/JSTS.2012.12.2.168
This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.
Block-Based Predictive Watershed Transform for Parallel Video Segmentation
Jang, Jung-Whan ; Lee, Hyuk-Jae ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 175~185
DOI : 10.5573/JSTS.2012.12.2.175
Predictive watershed transform is a popular object segmentation algorithm which achieves a speed-up by identifying image regions that are different from the previous frame and performing object segmentation only for those regions. However, incorrect segmentation is often generated by the predictive watershed transform which uses only local information in merge-split decision on boundary regions. This paper improves the predictive watershed transform to increase the accuracy of segmentation results by using the additional information about the root of boundary regions. Furthermore, the proposed algorithm is processed in a block-based manner such that an image frame is decomposed into blocks and each block is processed independently of the other blocks. The block-based approach makes it easy to implement the algorithm in hardware and also permits an extension for parallel execution. Experimental results show that the proposed watershed transform produces more accurate segmentation results than the predictive watershed transform.
An Optimized Stacked Driver for Synchronous Buck Converter
Lee, Dong-Keon ; Lee, Sung-Chul ; Jeong, Hang-Geun ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 186~192
DOI : 10.5573/JSTS.2012.12.2.186
Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-
CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.
A Real-time Compact Structured-light based Range Sensing System
Hong, Byung-Joo ; Park, Chan-Oh ; Seo, Nam-Seok ; Cho, Jun-Dong ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 193~202
DOI : 10.5573/JSTS.2012.12.2.193
In this paper, we propose a new approach for compact range sensor system for real-time robot applications. Instead of using off-the-shelf camera and projector, we devise a compact system with a CMOS image-sensor and a DMD (Digital Micro-mirror Device) that yields smaller dimension (
) and lighter weight (500g). We also realize one chip hard-wired processing of projection of structured-light and computing the range by exploiting correspondences between CMOS images-ensor and DMD. This application-specific chip processing is implemented on an FPGA in real-time. Our range acquisition system performs 30 times faster than the same implementation in software. We also devise an efficient methodology to identify a proper light intensity to enhance the quality of range sensor and minimize the decoding error. Our experimental results show that the total-error is reduced by 16% compared to the average case.
2-D Large Inverse Transform (16×16, 32×32) for HEVC (High Efficiency Video Coding)
Park, Jong-Sik ; Nam, Woo-Jin ; Han, Seung-Mok ; Lee, Seong-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 203~211
DOI : 10.5573/JSTS.2012.12.2.203
This paper proposes a
inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of
suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18
technology shows about 300 MHz frequency and 287 Kgates area, which can process 4K (
)@ 30 fps image.
A Platform-Based SoC Design for Real-Time Stereo Vision
Yi, Jong-Su ; Park, Jae-Hwa ; Kim, Jun-Seong ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 212~218
DOI : 10.5573/JSTS.2012.12.2.212
A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.
Implementation of Electrochemical Methods for Metrology and Analysis of Nano Electronic Structures of Deep Trench DRAM
Zeru, Tadios Tesfu ; Schroth, Stephan ; Kuecher, Peter ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 219~229
DOI : 10.5573/JSTS.2012.12.2.219
In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.
Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications
Lee, Jae-Sung ; Cho, Seong-Jae ; Park, Byung-Gook ; Harris, James S. Jr. ; Kang, In-Man ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 230~239
DOI : 10.5573/JSTS.2012.12.2.230
In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS
Debug Port Protection Mechanism for Secure Embedded Devices
Park, Keun-Young ; Yoo, Sang-Guun ; Kim, Ju-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 12, issue 2, 2012, Pages 240~253
DOI : 10.5573/JSTS.2012.12.2.240
In this paper we propose a protection mechanism for the debug port. While debug ports are useful tools for embedded device development and maintenance, they can also become potential attack tools for device hacking in case their usage is permitted to hackers with malicious intentions. The proposed approach prevents illicit use of debug ports by controlling access through user authentication, where the device generates and issues authentication token only to the server-authenticated users. An authentication token includes user access information which represents the user`s permitted level of access and the maximum number of authentications allowed using the token. The device authenticates the user with the token and grants limited access based on the user`s access level. The proposed approach improves the degree of overall security by removing the need to expose the device`s secret key. Availability is also enhanced by not requiring server connection after the initial token generation and further by supporting flexible token transfer among predefined device groups. Low implementation cost is another benefit of the proposed approach, enabling it to be adopted to a wide range of environments in demand of debug port protection.