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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 13, Issue 6 - Dec 2013
Volume 13, Issue 5 - Oct 2013
Volume 13, Issue 4 - Aug 2013
Volume 13, Issue 3 - Jun 2013
Volume 13, Issue 2 - Apr 2013
Volume 13, Issue 1 - Feb 2013
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Sensitivity Alterable Biosensor Based on Gated Lateral BJT for CRP Detection
Yuan, Heng ; Kang, Byoung-Ho ; Lee, Jae-Sung ; Jeong, Hyun-Min ; Yeom, Se-Hyuk ; Kim, Kyu-Jin ; Kwon, Dae-Hyuk ; Kang, Shin-Won ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 1~7
DOI : 10.5573/JSTS.2013.13.1.001
In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.
An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure
Byun, Yong Ki ; Park, Jong Kang ; Kwon, Soongyu ; Kim, Jong Tae ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 8~14
DOI : 10.5573/JSTS.2013.13.1.008
A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.
AlN Based RF MEMS Tunable Capacitor with Air-Suspended Electrode with Two Stages
Cheon, Seong J. ; Jang, Woo J. ; Park, Hyeon S. ; Yoon, Min K. ; Park, Jae Y. ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 15~21
DOI : 10.5573/JSTS.2013.13.1.015
In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.
Investigation on Suppression of Nickel-Silicide Formation By Fluorocarbon Reactive Ion Etch (RIE) and Plasma-Enhanced Deposition
Kim, Hyun Woo ; Sun, Min-Chul ; Lee, Jung Han ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 22~27
DOI : 10.5573/JSTS.2013.13.1.022
Detailed study on how the plasma process during the sidewall spacer formation suppresses the formation of silicide is done. In non-patterned wafer test, it is found that both fluorocarbon reactive ion etch (RIE) and TEOS plasma-enhanced deposition processes modify the Si surface so that the silicide reaction is chemically inhibited or suppressed. In order to investigate the cause of the chemical modification, we analyze the elements on the silicon surface through Auger Electron Spectroscopy (AES). From the AES result, it is found that the carbon induces chemical modification which blocks the reaction between silicon and nickel. Thus, protecting the surface from the carbon-containing plasma process prior to nickel deposition appears critical in successful silicide formation.
Analytic Model of Spin-Torque Oscillators (STO) for Circuit-Level Simulation
Ahn, Sora ; Lim, Hyein ; Shin, Hyungsoon ; Lee, Seungjun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 28~33
DOI : 10.5573/JSTS.2013.13.1.028
Spin-torque oscillators (STO) is a new device that can be used as a tunable microwave source in various wireless devices. Spin-transfer torque effect in magnetic multilayered nanostructure can induce precession of magnetization when bias current and external magnetic field are properly applied, and a microwave signal is generated from that precession. We proposed a semi-empirical circuit-level model of an STO in previous work. In this paper, we present a refined STO model which gives more accuracy by considering physical phenomena in the calculation of effective field. Characteristics of the STO are expressed as functions of external magnetic field and bias current in Verilog-A HDL such that they can be simulated with circuit-level simulators such as Hspice. The simulation results are in good agreement with the experimental data.
A Face-Detection Postprocessing Scheme Using a Geometric Analysis for Multimedia Applications
Jang, Kyounghoon ; Cho, Hosang ; Kim, Chang-Wan ; Kang, Bongsoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 34~42
DOI : 10.5573/JSTS.2013.13.1.034
Human faces have been broadly studied in digital image and video processing fields. An appearance-based method, the adaptive boosting learning algorithm using integral image representations has been successfully employed for face detection, taking advantage of the feature extraction's low computational complexity. In this paper, we propose a face-detection postprocessing method that equalizes instantaneous facial regions in an efficient hardware architecture for use in real-time multimedia applications. The proposed system requires low hardware resources and exhibits robust performance in terms of the movements, zooming, and classification of faces. A series of experimental results obtained using video sequences collected under dynamic conditions are discussed.
Characterization of Density-of-States in Polymer-based Organic Thin Film Transistors and Implementation into TCAD Simulator
Kim, Jaehyeong ; Jang, Jaeman ; Bae, Minkyung ; Lee, Jaewook ; Kim, Woojoon ; Hur, Inseok ; Jeong, Hyun Kwang ; Kim, Dong Myong ; Kim, Dae Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 43~47
DOI : 10.5573/JSTS.2013.13.1.043
In this work, we report extraction of the density-of-states (DOS) in polymer-based organic thin film transistors through the multi-frequency C-V spectroscopy. Extracted DOS is implemented into a TCAD simulator and obtained a consistent output curves with non-linear characteristics considering the contact resistance effect. We employed a Schottky contact model for the source and drain to fully reproduce a strong nonlinearity with proper physical mechanisms in the output characteristics even under a very small drain biases. For experimental verification of the model and extracted DOS, 2 different OTFTs (P3HT and PQT-12) are employed. By controlling the Schottky contact model parameters in the TCAD simulator, we accurately reproduced the nonlinearity in the output characteristics of OTFT.
A Photovoltaic Power Management System using a Luminance-Controlled Oscillator for USN Applications
Jeong, Ji-Eun ; Bae, Jun-Han ; Lee, Jinwoong ; Lee, Caroline Sunyong ; Chun, Jung-Hoon ; Kwon, Kee-Won ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 48~57
DOI : 10.5573/JSTS.2013.13.1.048
This paper presents a power management system of the dye-sensitized solar cell (DSSC) for ubiquitous sensor network (USN) applications. The charge pump with a luminance-controlled oscillator regulates the load impedance of the DSSC to track the maximum power point (MPP) under various light intensities. The low drop-out regulator with a hysteresis comparator supplies intermittent power pulses that are wide enough for USN to communicate with a host transponder even under dim light conditions. With MPP tracking, approximately 50% more power is harvested over a wide range of light intensity. The power management system fabricated using
CMOS technology works with DSSC to provide power pulses of
. The duration of pulses is almost constant around
(6.5 nJ/pulse), while the pulse spacing is inversely proportional to the light intensity.
PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch
Choi, Jun-Myung ; Jung, Chul-Moon ; Min, Kyeong-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 58~64
DOI : 10.5573/JSTS.2013.13.1.058
In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than
, respectively, at
. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.
New GGNMOS I/O Cell Array for Improved Electrical Overstress Robustness
Pang, Yon-Sup ; Kim, Youngju ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 65~70
DOI : 10.5573/JSTS.2013.13.1.065
3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.
An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring
Yi, Hyunbean ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 71~78
DOI : 10.5573/JSTS.2013.13.1.071
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.
An Arbitrary Waveform 16 Channel Neural Stimulator with Adaptive Supply Regulator in 0.35 ㎛ HV CMOS for Visual Prosthesis
Seo, Jindeok ; Lim, Kyomuk ; Lee, Sangmin ; Ahn, Jaehyun ; Hong, Seokjune ; Yoo, Hyungjung ; Jung, Sukwon ; Park, Sunkil ; Cho, Dong-Il Dan ; Ko, Hyoungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 1, 2013, Pages 79~86
DOI : 10.5573/JSTS.2013.13.1.079
We describe a neural stimulator front-end with arbitrary stimulation waveform generator and adaptive supply regulator (ASR) for visual prosthesis. Each pixel circuit generates arbitrary current waveform with 5 bit programmable amplitude. The ASR provides the internal supply voltage regulated to the minimum required voltage for stimulation. The prototype is implemented in
CMOS with HV option and occupies