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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 13, Issue 6 - Dec 2013
Volume 13, Issue 5 - Oct 2013
Volume 13, Issue 4 - Aug 2013
Volume 13, Issue 3 - Jun 2013
Volume 13, Issue 2 - Apr 2013
Volume 13, Issue 1 - Feb 2013
Selecting the target year
A Fast Low Dropout Regulator with High Slew Rate and Large Unity-Gain Bandwidth
Ko, Younghun ; Jang, Yeongshin ; Han, Sok-Kyun ; Lee, Sang-Gug ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 263~271
DOI : 10.5573/JSTS.2013.13.4.263
A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in
high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for
output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV,
, and higher than 1 MHz, respectively.
A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS
Park, Hyung-Gu ; Kim, Hongjin ; Lee, Dong-Soo ; Yu, Chang-Zhi ; Ku, Hyunchul ; Lee, Kang-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 272~281
DOI : 10.5573/JSTS.2013.13.4.272
This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in
1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is
. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.
A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile
Oh, Seung-Wook ; Park, Hyung-Min ; Moon, Yong-Hwan ; Kang, Jin-Ku ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 282~290
DOI : 10.5573/JSTS.2013.13.4.282
This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a
Application-aware Design Parameter Exploration of NAND Flash Memory
Bang, Kwanhu ; Kim, Dong-Gun ; Park, Sang-Hoon ; Chung, Eui-Young ; Lee, Hyuk-Jun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 291~302
DOI : 10.5573/JSTS.2013.13.4.291
NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.
Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Zhang, Changchun ; Li, Ming ; Wang, Zhigong ; Yin, Kuiying ; Deng, Qing ; Guo, Yufeng ; Cao, Zhengjun ; Liu, Leilei ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 303~317
DOI : 10.5573/JSTS.2013.13.4.303
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard
CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier
Han, Seok-Kyun ; Nguyen, Huy-Hieu ; Lee, Sang-Gug ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 318~330
DOI : 10.5573/JSTS.2013.13.4.318
This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in
CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than
dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of
and consumes only 1.3 mA from the 1.8 V supply.
Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT
Bhattacharya, Monika ; Jogi, Jyotika ; Gupta, R.S. ; Gupta, Mridula ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 331~341
DOI : 10.5573/JSTS.2013.13.4.331
In the present work, the effect of the gate-to-drain capacitance (
) on the noise performance of a symmetric tied-gate
double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters (
which are obtained incorporating the effect of
), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.
Quantum Modeling of Nanoscale Symmetric Double-Gate InAlAs/InGaAs/InP HEMT
Verma, Neha ; Gupta, Mridula ; Gupta, R.S. ; Jogi, Jyotika ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 342~354
DOI : 10.5573/JSTS.2013.13.4.342
The aim of this work is to investigate and study the quantum effects in the modeling of nanoscale symmetric double-gate InAlAs/InGaAs/InP HEMT (High Electron Mobility Transistor). In order to do so, the carrier concentration in InGaAs channel at gate lengths (
) 100 nm and 50 nm, are modelled by a density gradient model or quantum moments model. The simulated results obtained from the quantum moments model are compared with the available experimental results to show the accuracy and also with a semi-classical model to show the need for quantum modeling. Quantum modeling shows major variation in electron concentration profiles and affects the device characteristics. The two triangular quantum wells predicted by the semi-classical model seem to vanish in the quantum model as bulk inversion takes place. The quantum effects thus become essential to incorporate in nanoscale heterostructure device modeling.
A Wireless Intraocular Pressure Sensor with Variable Inductance Using a Ferrite Material
Kang, Byungjoo ; Hwang, Hoyong ; Lee, Soo Hyun ; Kang, Ji Yoon ; Park, Joung-Hu ; Seo, Chulhun ; Park, Changkun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 355~360
DOI : 10.5573/JSTS.2013.13.4.355
A wireless intraocular (IOP) pressure sensor based on micro electro mechanical system (MEMS) technology is proposed. The proposed IOP sensor uses variable inductance according to the external pressure. The proposed sensor is composed of two flexible membranes: a ferrite bottom part, an inductor, and a capacitor. The inductance of the sensor varies according to the external pressure. The resonance frequency of the sensor is also varied, and this frequency is detected using an external coil. The external coil is designed with an FR-4 printed circuit board. The feasibility of the proposed sensor structure using variable inductance to detect the external pressure is successfully demonstrated.
Full-Range Analytic Drain Current Model for Depletion-Mode Long-Channel Surrounding-Gate Nanowire Field-Effect Transistor
Yu, Yun Seop ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 361~366
DOI : 10.5573/JSTS.2013.13.4.361
A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.
An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates
Bhushan, Shiv ; Sarangi, Santunu ; Gopi, Krishna Saramekala ; Santra, Abirmoya ; Dubey, Sarvesh ; Tiwari, Pramod Kumar ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 367~380
DOI : 10.5573/JSTS.2013.13.4.367
In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium (
) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed
layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS
, a 2D device simulator from Silvaco Inc.
A New Resistance Model for a Schottky Barrier Diode in CMOS Including N-well Thickness Effect
Lee, Jaelin ; Kim, Suna ; Hong, Jong-Phil ; Lee, Sang-Gug ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 381~386
DOI : 10.5573/JSTS.2013.13.4.381
A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a
CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.
Hydrogen Plasma Characteristics for Photoresist Stripping Process in a Cylindrical Inductively Coupled Plasma
Yang, Seung-Kook ; Cho, Jung Hee ; Lee, Seong-Wook ; Lee, Chang-Won ; Park, Sang-Jong ; Chae, Hee-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 387~394
DOI : 10.5573/JSTS.2013.13.4.387
As the feature size of integrated circuits continues to decrease, the challenge of achieving an oxidation-free exposed layer after photoresist (PR) stripping is becoming a critical issue for semiconductor device fabrication. In this article, the hydrogen plasma characteristics in direct plasma and the PR stripping rate in remote plasma were studied using a
cylindrical inductively coupled plasma source. E mode, H mode and E-H mode transitions were observed, which were defined by matching the
and total impedance. In addition, the dependence of the E-H mode transition on pressure was examined and the corresponding plasma instability regions were identified. The plasma density and electron temperature increased gradually under the same process conditions. In contrast, the PR stripping rate decreased with increasing proportion of
gas in mixed
plasma. The decrease in concentration of reactive radicals for the removal of PR with increasing
gas flow rate suggests that NH radicals have a dominant effect as the main volatile product.
Use of In-Situ Optical Emission Spectroscopy for Leak Fault Detection and Classification in Plasma Etching
Lee, Ho Jae ; Seo, Dong-Sun ; May, Gary S. ; Hong, Sang Jeen ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 395~401
DOI : 10.5573/JSTS.2013.13.4.395
In-situ optical emission spectroscopy (OES) is employed for leak detection in plasma etching system. A misprocessing is reported for significantly reduced silicon etch rate with chlorine gas, and OES is used as a supplementary sensor to analyze the gas phase species that reside in the process chamber. Potential cause of misprocessing reaches to chamber O-ring wear out, MFC leaks, and/or leak at gas delivery line, and experiments are performed to funnel down the potential of the cause. While monitoring the plasma chemistry of the process chamber using OES, the emission trace for nitrogen species is observed at the chlorine gas supply. No trace of nitrogen species is found in other than chlorine gas supply, and we found that the amount of chlorine gas is slightly fluctuating. We successfully found the root cause of the reported misprocessing which may jeopardize the quality of thin film processing. Based on a quantitative analysis of the amount of nitrogen observed in the chamber, we conclude that the source of the leak is the fitting of the chlorine mass flow controller with the amount of around 2-5 sccm.
Mechanism and Application of NMOS Leakage with Intra-Well Isolation Breakdown by Voltage Contrast Detection
Chen, Hunglin ; Fan, Rongwei ; Lou, Hsiaochi ; Kuo, Mingsheng ; Huang, Yiping ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 402~409
DOI : 10.5573/JSTS.2013.13.4.402
An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.
Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application
Park, Byung Kyu ; Choi, Woo Young ; Cho, Eou Sik ; Cho, Il Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 4, 2013, Pages 410~414
DOI : 10.5573/JSTS.2013.13.4.410
We report the wet etching of titanium nickel (TiNi) films for the production of nano-electro-mechanical (NEM) device.
have been selected as sacrificial layers of TiNi metal and etched with polyethylene glycol and hydrofluoric acid (HF) mixed solution. Volume percentage of HF are varied from 10% to 35% and the etch rate of the
and TiNi are reported here. Within the various experiment results, 15% HF mixed polyethylene glycol solution show highest etch ratio between sacrificial layer and TiNi metal. Especially
films shows high etch ratio with TiNi films. Wet etching results are measured with SEM inspection. Therefore, this experiment provides a novel method for TiNi in the nano-electro-mechanical device.