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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 13, Issue 6 - Dec 2013
Volume 13, Issue 5 - Oct 2013
Volume 13, Issue 4 - Aug 2013
Volume 13, Issue 3 - Jun 2013
Volume 13, Issue 2 - Apr 2013
Volume 13, Issue 1 - Feb 2013
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Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme
Lee, Jeong-A ; Siddiqui, Zahid Ali ; Somasundaram, Natarajan ; Lee, Jeong-Gun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 415~422
DOI : 10.5573/JSTS.2013.13.5.415
In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.
A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level
Bae, Chang-Hyun ; Choi, Dong-Ho ; Ahn, Keun-Seon ; Yoo, Changsik ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 423~429
DOI : 10.5573/JSTS.2013.13.5.423
A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.
Design of a Fast Multi-Reference Frame Integer Motion Estimator for H.264/AVC
Byun, Juwon ; Kim, Jaeseok ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 430~442
DOI : 10.5573/JSTS.2013.13.5.430
This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video (
) in real-time at a 135 MHz clock speed with 5 reference frames.
New Encoding Method for Low Power Sequential Access ROMs
Cho, Seong-Ik ; Jung, Ki-Sang ; Kim, Sung-Mi ; You, Namhee ; Lee, Jong-Yeol ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 443~450
DOI : 10.5573/JSTS.2013.13.5.443
This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1`s, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.
An efficient LIN MCU design for In-Vehicle Networks
Yeon, Kyu-Bong ; Chong, Jong-Wha ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 451~458
DOI : 10.5573/JSTS.2013.13.5.451
This paper describes a design of LIN MCU using efficient memory accessing architecture which provides concurrent data and address fetch for faster communication. By using slew rate control it can reduce EMI emission while satisfying required communication specifications. To verify the efficiency of the LIN MCU, we developed a SoC and tested for several data packets. Measurements show that this LIN MCU improves network efficiency up to 17.19 % and response time up to 31.26 % for nominal cases. EMI radiation also can be reduced up to 10 dB.
A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier
Park, Geontae ; Kim, Hyungtak ; Kim, Jongsun ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 459~464
DOI : 10.5573/JSTS.2013.13.5.459
A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.
Low-Complexity Triple-Error-Correcting Parallel BCH Decoder
Yeon, Jaewoong ; Yang, Seung-Jun ; Kim, Cheolho ; Lee, Hanho ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 465~472
DOI : 10.5573/JSTS.2013.13.5.465
This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF(
), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.
An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique
Lee, Seongjoo ; Lee, Jangwoo ; Lee, Mun-Kyo ; Nah, Sun-Phil ; Song, Minkyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 473~481
DOI : 10.5573/JSTS.2013.13.5.473
A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is
(ADC core :
, calibration engine :
), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.
A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design
Choi, Minsoo ; Sim, Jae-Yoon ; Park, Hong-June ; Kim, Byungsub ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 482~491
DOI : 10.5573/JSTS.2013.13.5.482
This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher`s equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.
Influence of Series Resistance and Interface State Density on Electrical Characteristics of Ru/Ni/n-GaN Schottky structure
Reddy, M. Siva Pratap ; Kwon, Mi-Kyung ; Kang, Hee-Sung ; Kim, Dong-Seok ; Lee, Jung-Hee ; Reddy, V. Rajagopal ; Jang, Ja-Soon ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 492~499
DOI : 10.5573/JSTS.2013.13.5.492
We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (
) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The
and the series resistance (
) obtained from Cheung`s method are compared with modified Norde`s method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density (
) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density
as determined by Terman`s method is found to be
for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.
Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor
Gautam, Rajni ; Saxena, Manoj ; Gupta, R.S. ; Gupta, Mridula ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 500~510
DOI : 10.5573/JSTS.2013.13.5.500
In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.
Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs
Park, In Jun ; Shin, Changhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 511~515
DOI : 10.5573/JSTS.2013.13.5.511
A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (
), correlation length (
), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e.,
and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced
variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced
variation. The total random variation in
, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).
Study of Switching and Kirk Effects in InAlAs/InGaAs/InAlAs Double Heterojunction Bipolar Transistors
Mohiuddin, M. ; Sexton, J. ; Missous, M. ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 516~521
DOI : 10.5573/JSTS.2013.13.5.516
This paper investigates the two dominant but intertwined current blocking mechanisms of Switching and Kirk Effect in pure ternary InAlAs/InGaAs/InAlAs Double Heterojunction Bipolar Transistors (DHBTs). Molecular Beam Epitaxy (MBE) grown, lattice-matched samples have been investigated giving substantial experimental results and theoretical reasoning to explain the interplay between these two effects as the current density is increased up to and beyond the theoretical Kirk Effect limit for devices of emitter areas varying from
. Pure ternary InAlAs/InGaAs/InAlAs DHBTs are ideally suited for such investigations because, unless corrective measures are taken, these devices suffer from appreciable current blocking effect due to their large conduction band discontinuity of 0.5 eV and thus facilitating the observation of the two different physical phenomena. This enhanced understanding of the interplay between the Kirk and Switching effect makes the DHBT device design and optimization process more effective and efficient.
Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET
Baek, Ki-Ju ; Na, Kee-Yeol ; Park, Jeong-Hyeon ; Kim, Yeong-Seuk ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 522~529
DOI : 10.5573/JSTS.2013.13.5.522
In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments,
20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.
Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope
Najam, Faraz ; Kim, Sangsig ; Yu, Yun Seop ;
JSTS:Journal of Semiconductor Technology and Science, volume 13, issue 5, 2013, Pages 530~537
DOI : 10.5573/JSTS.2013.13.5.530
An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.