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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 14, Issue 6 - Dec 2014
Volume 14, Issue 5 - Oct 2014
Volume 14, Issue 4 - Aug 2014
Volume 14, Issue 3 - Jun 2014
Volume 14, Issue 2 - Apr 2014
Volume 14, Issue 1 - Feb 2014
Selecting the target year
Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching
Lee, Byeong-Il ; Geum, Jong Min ; Jung, Eun Sik ; Kang, Ey Goo ; Kim, Yong-Tae ; Sung, Man Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 263~267
DOI : 10.5573/JSTS.2014.14.3.263
Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.
A Finite Element Model for Bipolar Resistive Random Access Memory
Kim, Kwanyong ; Lee, Kwangseok ; Lee, Keun-Ho ; Park, Young-Kwan ; Choi, Woo Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 268~273
DOI : 10.5573/JSTS.2014.14.3.268
The forming, reset and set operation of bipolar resistive random access memory (RRAM) have been predicted by using a finite element (FE) model which includes interface effects. To the best of our knowledge, our bipolar RRAM model is applicable to realistic cell structure optimization because our model is based on the FE method (FEM) unlike precedent models.
Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology
Misra, Prasanna Kumar ; Qureshi, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 274~283
DOI : 10.5573/JSTS.2014.14.3.274
In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved
product (397 GHzV). As the
value is higher for low value of epi layer doping, higher supply voltage can be used to increase the
value of the HBT. At 1.8 V
product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV
product at 1.2 V
). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.
Energy-Efficient and High Performance CGRA-based Multi-Core Architecture
Kim, Yoonjin ; Kim, Heesun ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 284~299
DOI : 10.5573/JSTS.2014.14.3.284
Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.
Load-Balance-Independent High Efficiency Single-Inductor Multiple-Output (SIMO) DC-DC Converters
Ko, Younghun ; Jang, Yeongshin ; Han, Sok-Kyun ; Lee, Sang-Gug ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 300~312
DOI : 10.5573/JSTS.2014.14.3.300
A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-
CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.
Polar Transmitter with Differential DSM Phase and Digital PWM Envelope
Zhou, Bo ; Liu, Shuli ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 313~321
DOI : 10.5573/JSTS.2014.14.3.313
A low-power low-cost polar transmitter for EDGE is designed in
CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.
Efficient and Low-Cost Metal Revision Techniques for Post Silicon Repair
Lee, Sungchul ; Shin, Hyunchul ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 322~330
DOI : 10.5573/JSTS.2014.14.3.322
New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.
A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique
Moon, Yongsam ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 331~338
DOI : 10.5573/JSTS.2014.14.3.331
A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-
CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.
A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps
Jung, Jin-Woo ; Koo, Yong-Seo ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 339~344
DOI : 10.5573/JSTS.2014.14.3.339
This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD)
. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately
. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.
Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC
Song, Jaehoon ; Jung, Jihun ; Kim, Dooyoung ; Park, Sungju ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 345~355
DOI : 10.5573/JSTS.2014.14.3.345
Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.
New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing
Truong, Son Ngoc ; Min, Kyeong-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 3, 2014, Pages 356~363
DOI : 10.5573/JSTS.2014.14.3.356
In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.