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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 14, Issue 6 - Dec 2014
Volume 14, Issue 5 - Oct 2014
Volume 14, Issue 4 - Aug 2014
Volume 14, Issue 3 - Jun 2014
Volume 14, Issue 2 - Apr 2014
Volume 14, Issue 1 - Feb 2014
Selecting the target year
An Adaptively Segmented Forward Problem Based Non-Blind Deconvolution Technique for Analyzing SRAM Margin Variation Effects
Somha, Worawit ; Yamauchi, Hiroyuki ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 365~375
DOI : 10.5573/JSTS.2014.14.4.365
This paper proposes an abnormal V-shaped-error-free non-blind deconvolution technique featuring an adaptively segmented forward-problem based iterative deconvolution (ASDCN) process. Unlike the algebraic based inverse operations, this eliminates any operations of differential and division by zero to successfully circumvent the issue on the abnormal V-shaped error. This effectiveness has been demonstrated for the first time with applying to a real analysis for the effects of the Random Telegraph Noise (RTN) and/or Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. It has been shown that the proposed ASDCN technique can reduce its relative errors of RTN deconvolution by
fold, which are good enough for avoiding the abnormal ringing errors in the RTN deconvolution process. This enables to suppress the cdf error of the convolution of the RTN with the RDF (i.e., fail-bit-count error) to
error for the conventional algorithm.
A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks
Lee, Seongjoo ; Lee, Jangwoo ; Song, Minkyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 376~382
DOI : 10.5573/JSTS.2014.14.4.376
In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is
and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.
Implementation of Excitatory CMOS Neuron Oscillator for Robot Motion Control Unit
Lu, Jing ; Yang, Jing ; Kim, Yong-Bin ; Ayers, Joseph ; Kim, Kyung Ki ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 383~390
DOI : 10.5573/JSTS.2014.14.4.383
This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is
including I/O pads.
Algorithmic GPGPU Memory Optimization
Jang, Byunghyun ; Choi, Minsu ; Kim, Kyung Ki ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 391~406
DOI : 10.5573/JSTS.2014.14.4.391
The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.
High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement
Byun, Wooseok ; Kim, Hyeji ; Kim, Ji-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 407~418
DOI : 10.5573/JSTS.2014.14.4.407
As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.
7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes
Jung, Yong-Min ; Chung, Chul-Ho ; Jung, Yun-Ho ; Kim, Jae-Seok ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 419~426
DOI : 10.5573/JSTS.2014.14.4.419
This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.
Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO
Nam, Hyohyun ; Park, Seulki ; Shin, Changhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 427~435
DOI : 10.5573/JSTS.2014.14.4.427
Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of
(a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with
, and the VSTI region is filled with
) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with
, and the STI region is filled with
) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate (
) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest
value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.
A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design
Yoon, Myungchul ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 436~442
DOI : 10.5573/JSTS.2014.14.4.436
A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.
Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers
Jung, Hyun-Yong ; Youn, Jin-Sung ; Choi, Woo-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 443~450
DOI : 10.5573/JSTS.2014.14.4.443
This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84
and 12 GHz, respectively. 20-Gb/s
electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than
. The receiver circuit has chip area of
and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.
Compact Model of a pH Sensor with Depletion-Mode Silicon-Nanowire Field-Effect Transistor
Yu, Yun Seop ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 451~456
DOI : 10.5573/JSTS.2014.14.4.451
A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson`s equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.
A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops
Choi, Young-Shig ; Park, Jong-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 457~462
DOI : 10.5573/JSTS.2014.14.4.457
This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal
CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.
Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface
Seong, Ki-Hwan ; Lim, Ji-Hoon ; Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 463~470
DOI : 10.5573/JSTS.2014.14.4.463
A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.
EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation
Kim, Namkyoung ; Hwang, Jisoo ; Kim, SoYoung ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 471~477
DOI : 10.5573/JSTS.2014.14.4.471
In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.
Investigation of Buffer Traps in AlGaN/GaN Heterostructure Field-Effect Transistors Using a Simple Test Structure
Jang, Seung Yup ; Shin, Jong-Hoon ; Hwang, Eu Jin ; Choi, Hyo-Seung ; Jeong, Hun ; Song, Sang-Hun ; Kwon, Hyuck-In ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 478~483
DOI : 10.5573/JSTS.2014.14.4.478
We propose a new method which can extract the information about the electronic traps in the semi-insulating GaN buffer of AlGaN/GaN heterostructure field-effect transistors (HFETs) using a simple test structure. The proposed method has a merit in the easiness of fabricating the test structure. Moreover, the electric fields inside the test structure are very similar to those inside the actual transistor, so that we can extract the information of bulk traps which directly affect the current collapse behaviors of AlGaN/GaN HEFTs. By applying the proposed method to the GaN buffer structures with various unintentionally doped GaN channel thicknesses, we conclude that the incorporated carbon into the GaN back barrier layer is the dominant origin of the bulk trap which affects the current collapse behaviors of AlGaN/GaN HEFTs.
A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL
Kavala, Anil ; Bae, Woorham ; Kim, Sungwoo ; Hong, Gi-Moon ; Chi, Hankyu ; Kim, Suhwan ; Jeong, Deog-Kyoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 484~494
DOI : 10.5573/JSTS.2014.14.4.484
We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of
at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.
Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode
Bouangeune, Daoheung ; Choi, Sang-Sik ; Cho, Deok-Ho ; Shim, Kyu-Hwan ; Chang, Sung-Yong ; Leem, See-Jong ; Choi, Chel-Jong ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 4, 2014, Pages 495~502
DOI : 10.5573/JSTS.2014.14.4.495
Fast recovery diodes (FRDs) were developed using the
epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, <
A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to
kV of HBM and
kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current,
, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.