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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 14, Issue 6 - Dec 2014
Volume 14, Issue 5 - Oct 2014
Volume 14, Issue 4 - Aug 2014
Volume 14, Issue 3 - Jun 2014
Volume 14, Issue 2 - Apr 2014
Volume 14, Issue 1 - Feb 2014
Selecting the target year
On-State Resistance Instability of Programmed Antifuse Cells during Read Operation
Han, Jae Hwan ; Lee, Hyunjin ; Kim, Wansoo ; Yoon, Gyuhan ; Choi, Woo Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 503~507
DOI : 10.5573/JSTS.2014.14.5.503
The on-state resistance (
) instability of standard complementary metal-oxide-semiconductor (CMOS) antifuse cells has been observed for the first time by using acceleration factors: stress current and ambient temperature. If the program current is limited, the
increases as time passes during read operation.
Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors
Kim, Sung Yoon ; Seo, Jae Hwa ; Yoon, Young Jun ; Yoo, Gwan Min ; Kim, Young Jae ; Eun, Hye Rim ; Kang, Hye Su ; Kim, Jungjoon ; Cho, Seongjae ; Lee, Jung-Hee ; Kang, In Man ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 508~517
DOI : 10.5573/JSTS.2014.14.5.508
We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (
) and height (
) of the fin as well as the channel doping concentration (
). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.
Substrate Doping Concentration Dependence of Electron Mobility Enhancement in Uniaxial Strained (110)/<110> nMOSFETs
Sun, Wookyung ; Choi, Sujin ; Shin, Hyungsoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 518~524
DOI : 10.5573/JSTS.2014.14.5.518
The substrate doping concentration dependence of strain-enhanced electron mobility in (110)/<110> nMOSFETs is investigated by using a self-consistent Schr
dinger-Poisson solver. The electron mobility model includes Coulomb, phonon, and surface roughness scattering. The calculated results show that, in contrast to (100)/<110> case, the longitudinal tensile strain-induced electron mobility enhancement on the (110)/<110> can be increased at high substrate doping concentration.
Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance
An, TaeYoon ; Choe, KyeongKeun ; Kwon, Kee-Won ; Kim, SoYoung ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 525~536
DOI : 10.5573/JSTS.2014.14.5.525
Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (
). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.
Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect
Yang, Hyung Jun ; Song, Yun-Heub ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 537~542
DOI : 10.5573/JSTS.2014.14.5.537
The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage (
) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.
Characterization of Dielectric Relaxation and Reliability of High-k MIM Capacitor Under Constant Voltage Stress
Kwak, Ho-Young ; Kwon, Sung-Kyu ; Kwon, Hyuk-Min ; Sung, Seung-Yong ; Lim, Su ; Kim, Choul-Young ; Lee, Ga-Won ; Lee, Hi-Deok ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 543~548
DOI : 10.5573/JSTS.2014.14.5.543
In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator-metal (MIM) capacitors using
sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric.
A Highly Power-Efficient Single-Inductor Multiple-Outputs (SIMO) DC-DC Converter with Gate Charge Sharing Method
Nam, Ki-Soo ; Seo, Whan-Seok ; Ahn, Hyun-A ; Jung, Young-Ho ; Hong, Seong-Kwan ; Kwon, Oh-Kyong ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 549~556
DOI : 10.5573/JSTS.2014.14.5.549
This paper proposes a highly power-efficient single-inductor multiple-outputs (SIMO) DC-DC converter with a gate charge sharing method in which gate charges of output switches are shared to improve the power efficiency and to reduce the switching power loss. The proposed converter was fabricated by using a
CMOS process technology with high voltage devices of 5 V. The input voltage range of the converter is from 2.8 V to 4.2 V, which is based on a single cell lithium-ion battery, and the output voltages are 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V. Using the proposed gate charge sharing method, the maximum power efficiency is measured to be 87.2% at the total output current of 450 mA. The measured power efficiency improved by 2.1% compared with that of the SIMO DC-DC converter without the proposed gate charge sharing method.
Effect of Basal-plane Stacking Faults on X-ray Diffraction of Non-polar (1120) a-plane GaN Films Grown on (1102) r-plane Sapphire Substrates
Kim, Ji Hoon ; Hwang, Sung-Min ; Baik, Kwang Hyeon ; Park, Jung Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 557~565
DOI : 10.5573/JSTS.2014.14.5.557
We report the effect of basal-plane stacking faults (BSFs) on X-ray diffraction (XRD) of non-polar (11
0) a-plane GaN films with different
coverage and increased three-dimensional (3D) to two-dimensional (2D) transition stages substantially reduce BSF density. It was revealed that the Si-doping profile in the Si-doped GaN layer was unaffected by the introduction of a
interlayer. The smallest in-plane anisotropy of the (11
-scan widths was found in the sample with multiple
layers, and this finding can be attributed to the relatively isotropic GaN mosaic resulting from the increase in the 3D-2D growth step. Williamson-Hall (WH) analysis of the (h0
0) series of diffractions was employed to determine the c-axis lateral coherence length (LCL) and to estimate the mosaic tilt. The c-axis LCLs obtained from WH analyses of the present study's representative a-plane GaN samples were well correlated with the BSF-related results from both the off-axis XRD
-scan and transmission electron microscopy (TEM). Based on WH and TEM analyses, the trends in BSF densities were very similar, even though the BSF densities extracted from LCLs indicated that the values were reduced by a factor of about twenty.
A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory
Kim, Yoon ; Seo, Joo Yun ; Lee, Sang-Ho ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 566~571
DOI : 10.5573/JSTS.2014.14.5.566
Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the
variation among cells and reduce the total programming time.
Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique
Kim, Hyun Woo ; Kim, Jong Pil ; Kim, Sang Wan ; Sun, Min-Chul ; Kim, Garam ; Kim, Jang Hyun ; Park, Euyhwan ; Kim, Hyungjin ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 572~578
DOI : 10.5573/JSTS.2014.14.5.572
In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.
A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging
Cho, Seong-Eun ; Um, Ji-Yong ; Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 579~587
DOI : 10.5573/JSTS.2014.14.5.579
This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].
Reduction of Current Crowding in InGaN-based Blue Light-Emitting Diodes by Modifying Metal Contact Geometry
Kim, Garam ; Kim, Jang Hyun ; Park, Euyhwan ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 588~593
DOI : 10.5573/JSTS.2014.14.5.588
Current crowding problem can worsen the internal quantum efficiency and the negative-voltage ESD of InGaN-based LEDs. In this paper, by using photon emission microscope and thermal emission microscope measurement, we confirmed that the electric field and the current of the InGaN-based LED sample are crowded in specific regions where the distance between p-type metal contact and n-type metal contact is shorter than other regions. To improve this crowding problem of electric field and current, modified metal contact geometry having uniform distance between the two contacts is proposed and verified by a numerical simulation. It is confirmed that the proposed structure shows better current spreading, resulting in higher internal quantum efficiency and reduced reverse leakage current.
Pixel Circuit with Threshold Voltage Compensation using a-IGZO TFT for AMOLED
Lee, Jae Pyo ; Hwang, Jun Young ; Bae, Byung Seong ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 594~600
DOI : 10.5573/JSTS.2014.14.5.594
A threshold voltage compensation pixel circuit was developed for active-matrix organic light emitting diodes (AMOLEDs) using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO-TFTs). Oxide TFTs are n-channel TFTs; therefore, we developed a circuit for the n-channel TFT characteristics. The proposed pixel circuit was verified and proved by circuit analysis and circuit simulations. The proposed circuit was able to compensate for the threshold voltage variations of the drive TFT in AMOLEDs. The error rate of the OLED current for a threshold voltage change of 3 V was as low as 1.5%.
Device Performances Related to Gate Leakage Current in Al
Kim, Do-Kywn ; Sindhuri, V. ; Kim, Dong-Seok ; Jo, Young-Woo ; Kang, Hee-Sung ; Jang, Young-In ; Kang, In Man ; Bae, Youngho ; Hahm, Sung-Ho ; Lee, Jung-Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 601~608
DOI : 10.5573/JSTS.2014.14.5.601
In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of
gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to
from the value of
of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin
layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited
layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nm-thick
gate insulator exhibited extremely low gate leakage current of
, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high
. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick
layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick
layer due to thinner
layer, as expected. The device with 10 nm-thick
layer, however, showed very high gate leakage current of
due to poly-crystallization of the
layer during the high-temperature RTP, which led to very poor performances.
Fringe Field Effects on Transient Characteristics of Nano-Electromechanical (NEM) Nonvolatile Memory Cells
Han, Boram ; Choi, Woo Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 609~614
DOI : 10.5573/JSTS.2014.14.5.609
The fringe field effects on the transient characteristics of nano-electromechanical (NEM) memory cells have been discussed by using an analytical model. The influence of fringe field becomes stronger as the size of a cell decreases. By using the proposed model, the dependency of NEM memory transient characteristics on cell parameters has been evaluated.
Quantum Transport Simulations of CNTFETs: Performance Assessment and Comparison Study with GNRFETs
Wang, Wei ; Wang, Huan ; Wang, Xueying ; Li, Na ; Zhu, Changru ; Xiao, Guangran ; Yang, Xiao ; Zhang, Lu ; Zhang, Ting ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 615~624
DOI : 10.5573/JSTS.2014.14.5.615
In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger band-structure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMG-CNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS'10 requirements better than CNTs.
Compact Power-on Reset Circuit Using a Switched Capacitor
Seong, Kwang-Su ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 625~631
DOI : 10.5573/JSTS.2014.14.5.625
We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a
Wafer-Level Packaged MEMS Resonators with a Highly Vacuum-Sensitive Quality Factor
Kang, Seok Jin ; Moon, Young Soon ; Son, Won Ho ; Choi, Sie Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 632~639
DOI : 10.5573/JSTS.2014.14.5.632
Mechanical stress and the vacuum level are the two main factors dominating the quality factor of a resonator operated in the vacuum range 1 mTorr to 10 Torr. This means that if the quality factor of a resonator is very insensitive to the mechanical stress in the vacuum range, it is sensitive to mainly the ambient vacuum level. In this paper, a wafer-level packaged MEMS resonator with a highly vacuum-sensitive quality factor is presented. The proposed device is characterized by a package with out-of-plane symmetry and a suspending structure with only a single anchor. Out-of-plane symmetry helps prevent deformation of the packaged device due to thermal mismatch, and a single-clamped structure facilitates constraint-free displacement. As a result, the proposed device is very insensitive to mechanical stress and is sensitive to mainly the ambient vacuum level. The average quality factors of the devices packaged under pressures of 50, 100, and 200 mTorr were 4987, 3415, and 2127, respectively. The results demonstrated the high controllability of the quality factor by vacuum adjustment. The mechanical robustness of the quality factor was confirmed by comparing the quality factors before and after high-temperature storage. Furthermore, through more than 50 days of monitoring, the stability of the quality factor was also certified.
Reducing Test Power and Improving Test Effectiveness for Logic BIST
Wang, Weizheng ; Cai, Shuo ; Xiang, Lingyun ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 640~648
DOI : 10.5573/JSTS.2014.14.5.640
Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.
A Performance Analysis for Interconnections of 3D ICs with Frequency-Dependent TSV Model in S-parameter
Han, Ki Jin ; Lim, Younghyun ; Kim, Youngmin ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 649~657
DOI : 10.5573/JSTS.2014.14.5.649
In this study, the effects of the frequency-dependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is composed of 32-nm CMOS inverter drivers and receivers connected through TSVs. The frequency-domain model of TSVs is extracted in S-parameter from a 3D electromagnetic (EM) method, where the dimensional variation effect of TSVs can be accurately considered for a comprehensive parameter sweep simulation. A parametric analysis shows that the propagation delay increases with the diameter and height of the TSVs but decreases with the pitch and liner thickness. We also investigate the crosstalk effect between TSVs by testing different signaling conditions. From the simulations, the worst signal integrity is observed when the signal experiences a simultaneously coupled transition in the opposite direction from the aggressor lines. Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.
A 16-channel Neural Stimulator IC with DAC Sharing Scheme for Artificial Retinal Prostheses
Seok, Changho ; Kim, Hyunho ; Im, Seunghyun ; Song, Haryong ; Lim, Kyomook ; Goo, Yong-Sook ; Koo, Kyo-In ; Cho, Dong-Il ; Ko, Hyoungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 658~665
DOI : 10.5573/JSTS.2014.14.5.658
The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard
1P6M process. The chip size except the I/O cells is
High Performance p-type SnO thin-film Transistor with SiO
Gate Insulator Deposited by Low-Temperature PECVD Method
U, Myeonghun ; Han, Young-Joon ; Song, Sang-Hun ; Cho, In-Tak ; Lee, Jong-Ho ; Kwon, Hyuck-In ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 666~672
DOI : 10.5573/JSTS.2014.14.5.666
We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal
, a plasma-enhanced chemical vapor deposition (PECVD)
, and a
. Among the devices, the one with the
exhibits the best electrical performance including a high field-effect mobility (
), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.
Low Specific On-resistance SOI LDMOS Device with P
P-top Layer in the Drift Region
Yao, Jia-Fei ; Guo, Yu-Feng ; Xu, Guang-Ming ; Hua, Ting-Ting ; Lin, Hong ; Xiao, Jian ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 673~681
DOI : 10.5573/JSTS.2014.14.5.673
In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped
region which is connected to the P-top layer in the drift region. The
region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel
-top device also present cost efficiency due to the fact that the
region can be fabricated together with the P-type body contact region without any additional mask.
Temperature-Dependent Instabilities of DC characteristics in AlGaN/GaN-on-Si Heterojunction Field Effect Transistors
Keum, Dong-Min ; Choi, Shinhyuk ; Kang, Youngjin ; Lee, Jae-Gil ; Cha, Ho-Young ; Kim, Hyungtak ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 682~687
DOI : 10.5573/JSTS.2014.14.5.682
We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage (
) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the
and the on-current were decreased. The on-current reduction was caused by the positive shift of the
and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.
Dynamic Slew-Rate Control for High Uniformity and Low Power in LCD Driver ICs
Choi, Sung-Pil ; Lee, Mira ; Jin, Jahoon ; Kwon, Kee-Won ; Chun, Jung-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 5, 2014, Pages 688~696
DOI : 10.5573/JSTS.2014.14.5.688
A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.