Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 14, Issue 6 - Dec 2014
Volume 14, Issue 5 - Oct 2014
Volume 14, Issue 4 - Aug 2014
Volume 14, Issue 3 - Jun 2014
Volume 14, Issue 2 - Apr 2014
Volume 14, Issue 1 - Feb 2014
Selecting the target year
SiC Based Single Chip Programmable AC to DC Power Converter
Pratap, Rajendra ; Agarwal, Vineeta ; Ravindra, Kumar Singh ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 697~705
DOI : 10.5573/JSTS.2014.14.6.697
A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only
. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.
Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-based Input Voltage Range Detection Circuit
Dae, Si ; Yoon, Kwang Sub ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 706~711
DOI : 10.5573/JSTS.2014.14.6.706
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.
A 32 nm NPN SOI HBT with Programmable Power Gain and 839 GHzV f
Misra, Prasanna Kumar ; Qureshi, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 712~717
DOI : 10.5573/JSTS.2014.14.6.712
The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V
has very high
product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).
A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors
Park, Jong Kang ; Moon, Jun Young ; Kim, Kyunghoon ; Yang, Youngoo ; Kim, Jong Tae ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 718~727
DOI : 10.5573/JSTS.2014.14.6.718
In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a
CMOS standard cell library.
Macro-Model of Magnetic Tunnel Junction for STT-MRAM including Dynamic Behavior
Kim, Kyungmin ; Yoo, Changsik ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 728~732
DOI : 10.5573/JSTS.2014.14.6.728
Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.
The Micro Pirani Gauge with Low Noise CDS-CTIA for In-Situ Vacuum Monitoring
Kim, Gyungtae ; Seok, Changho ; Kim, Taehyun ; Park, Jae Hong ; Kim, Heeyeoun ; Ko, Hyoungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 733~740
DOI : 10.5573/JSTS.2014.14.6.733
A resistive micro Pirani gauge using amorphous silicon (a-Si) thin membrane is proposed. The proposed Pirani gauge can be easily integrated with the other process-compatible membrane-type sensors, and can be applicable for in-situ vacuum monitoring inside the vacuum package without an additional process. The vacuum level is measured by the resistance changes of the membrane using the low noise correlated double sampling (CDS) capacitive trans-impedance amplifier (CTIA). The measured vacuum range of the Pirani gauge is 0.1 to 10 Torr. The sensitivity and non-linearity are measured to be 78 mV / Torr and 0.5% in the pressure range of 0.1 to 10 Torr. The output noise level is measured to be
in 0.5 Hz to 50 Hz, which is 41.2% smaller than conventional CTIA.
Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM
Park, Jaehyun ; Shin, Donghwa ; Chang, Naehyuck ; Lee, Hyung Gyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 741~749
DOI : 10.5573/JSTS.2014.14.6.741
Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.
Charge Controlled Meminductor Emulator
Sah, Maheshwar Pd. ; Budhathoki, Ram Kaji ; Yang, Changju ; Kim, Hyongsuk ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 750~754
DOI : 10.5573/JSTS.2014.14.6.750
Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.
Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs
Kwon, Min-Woo ; Kim, Hyungjin ; Park, Jungjin ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 755~759
DOI : 10.5573/JSTS.2014.14.6.755
We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.
A 256-Radix Crossbar Switch Using Mux-Matrix-Mux Folded-Clos Topology
Lee, Sung-Joon ; Kim, Jaeha ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 760~767
DOI : 10.5573/JSTS.2014.14.6.760
This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of
Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp
Yu, Sang Dae ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 768~776
DOI : 10.5573/JSTS.2014.14.6.768
Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the
A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process
Park, Hyung-Gu ; Jang, Jeong-A ; Cho, Sung Hun ; Lee, Juri ; Kim, Sang-Yun ; Tiwari, Honey Durga ; Pu, Young Gun ; Hwang, Keum Cheol ; Yang, Youngoo ; Lee, Kang-Yoon ; Seo, Munkyo ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 777~788
DOI : 10.5573/JSTS.2014.14.6.777
This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using
BCD process with high power MOSFET options, and the die area is
. The power consumption of the charge pump itself is 79.13 mW when the output power is 415.45 mW at the high voltage mode, while it is 20.097 mW when the output power is 89.903 mW at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.
Improved Circuits for Single-photon Avalanche Photodiode Detectors
Kim, Kyunghoon ; Lee, Junan ; Song, Bongsub ; Burm, Jinwook ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 789~796
DOI : 10.5573/JSTS.2014.14.6.789
A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a
standard CMOS technology to verify the effectiveness of this technique with the chip area of only
, which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ns.
Novel Punch-through Diode Triggered SCR for Low Voltage ESD Protection Applications
Bouangeune, Daoheung ; Vilathong, Sengchanh ; Cho, Deok-Ho ; Shim, Kyu-Hwan ; Leem, See-Jong ; Choi, Chel-Jong ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 797~801
DOI : 10.5573/JSTS.2014.14.6.797
This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below
A, a low capacitance of
, and low triggering voltage of 8.5 V at
A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.
Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier
Ham, Junghyun ; Jung, Haeryun ; Bae, Jongsuk ; Lim, Wonseob ; Hwang, Keum Cheol ; Lee, Kang-Yoon ; Park, Cheon-Seok ; Yang, Youngoo ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 802~809
DOI : 10.5573/JSTS.2014.14.6.802
This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a
CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.
A Fast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator
Ha, Jung-Woo ; Park, Byeong-Ha ; Kong, Bai-Sun ; Chun, Jung-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 810~817
DOI : 10.5573/JSTS.2014.14.6.810
An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.
An X-Ku Band Distributed GaN LNA MMIC with High Gain
Kim, Dongmin ; Lee, Dong-Ho ; Sim, Sanghoon ; Jeon, Laurence ; Hong, Songcheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 818~823
DOI : 10.5573/JSTS.2014.14.6.818
A high-gain wideband low noise amplifier (LNA) using
Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of
and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.
Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes
Kim, Youngmin ; Lee, Jaemin ; Ryu, Myunghwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 14, issue 6, 2014, Pages 824~831
DOI : 10.5573/JSTS.2014.14.6.824
In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.