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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
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Journal DOI :
The Institute of Electronics Engineers of Korea
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Volume & Issues
Volume 15, Issue 6 - Dec 2015
Volume 15, Issue 5 - Oct 2015
Volume 15, Issue 4 - Aug 2015
Volume 15, Issue 3 - Jun 2015
Volume 15, Issue 2 - Apr 2015
Volume 15, Issue 1 - Feb 2015
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Stress-Sensors with High-Sensitivity Using the Combined Meandering-Patterns
Cho, Chun-Hyung ; Cha, Ho-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 1~6
DOI : 10.5573/JSTS.2015.15.1.001
In this work, the combined meandering-pattern stress-sensors were presented in order to achieve the high sensitivity of stress sensors. Compared to the previous works, which have been using the single meandering-pattern stress-sensors, the sensitivity was approximately observed to increase by 30%~70%. Also, in this paper, more simple and convenient stress-measurement method was presented.
Temperature Dependent Current Transport Mechanism in Graphene/Germanium Schottky Barrier Diode
Khurelbaatar, Zagarzusem ; Kil, Yeon-Ho ; Shim, Kyu-Hwan ; Cho, Hyunjin ; Kim, Myung-Jong ; Kim, Yong-Tae ; Choi, Chel-Jong ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 7~15
DOI : 10.5573/JSTS.2015.15.1.007
We have investigated electrical properties of graphene/Ge Schottky barrier diode (SBD) fabricated on Ge film epitaxially grown on Si substrate. When decreasing temperature, barrier height decreased and ideality factor increased, implying their strong temperature dependency. From the conventional Richardson plot, Richardson constant was much less than the theoretical value for n-type Ge. Assuming Gaussian distribution of Schottky barrier height with mean Schottky barrier height and standard deviation, Richardson constant extracted from the modified Richardson plot was comparable to the theoretical value for n-type Ge. Thus, the abnormal temperature dependent Schottky behavior of graphene/Ge SBD could be associated with a considerable deviation from the ideal thermionic emission caused by Schottky barrier inhomogeneities.
Forming Gas Post Metallization Annealing of Recessed AlGaN/GaN-on-Si MOSHFET
Lee, Jung-Yeon ; Park, Bong-Ryeol ; Lee, Jae-Gil ; Lim, Jongtae ; Cha, Ho-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 16~21
DOI : 10.5573/JSTS.2015.15.1.016
In this study, the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET were investigated. The device employed an ICPCVD
film as a gate oxide layer on which a Ni/Au gate was evaporated. The PMA process was carried out at
in forming gas ambient. It was found that the device instability was improved with significant reduction in interface trap density by forming gas PMA.
High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs
Lee, Junan ; Huang, Qiwei ; Kim, Kiwoon ; Kim, Kyunghoon ; Burm, Jinwook ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 22~28
DOI : 10.5573/JSTS.2015.15.1.022
This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a
An Oscillator and a Mixer for 140-GHz Heterodyne Receiver Front-End based on SiGe HBT Technology
Yoon, Daekeun ; Song, Kiryong ; Kaynak, Mehmet ; Tillack, Bernd ; Rieh, Jae-Sung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 29~34
DOI : 10.5573/JSTS.2015.15.1.029
This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.
Enhanced Photo Current in n-ZnO/p-Si Diode Via Embedded Ag Nanoparticles for the Solar Cell Application
Ko, Young-Uk ; Yun, Ho-Jin ; Jeong, Kwang-Seok ; Kim, Yu-Mi ; Yang, Seung-Dong ; Kim, Seong-Hyeon ; Kim, Jin-Sup ; An, Jin-Un ; Eom, Ki-Yun ; Lee, Hi-Deok ; Lee, Ga-Won ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 35~40
DOI : 10.5573/JSTS.2015.15.1.035
In this study, an n-ZnO/p-Si heterojunction diode with embedded Ag nanoparticles was fabricated to investigate the possible improvement of light trapping via the surface plasmon resonance effect for solar cell applications. The Ag nanoparticles were fabricated by the physical sputtering method. The acquired current-voltage curves and optical absorption spectra demonstrated that the application of Ag nanoparticles in the n-ZnO/p-Si interface increased the photo current, particularly in specific wavelength regions. The results indicate that the enhancement of the photo current was caused by the surface plasmon resonance effect generated by the Ag nanoparticles. In addition, minority carrier lifetime measurements showed that the recombination losses caused by the Ag nanoparticles were negligible. These results suggest that the embedding of Ag nanoparticles is a powerful method to improve the performance of n-ZnO/p-Si heterojunction solar cells.
A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si on the Thickness of the Antimony Interlayer for High Performance n-channel MOSFETs
Lee, Horyeong ; Li, Meng ; Oh, Jungwoo ; Lee, Hi-Deok ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 41~47
DOI : 10.5573/JSTS.2015.15.1.041
In this paper, the effective electron Schottky barrier height (
) of the Ni silicide/n-silicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective
is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective
of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs.
Efficient Kernel Integrity Monitor Design for Commodity Mobile Application Processors
Heo, Ingoo ; Jang, Daehee ; Moon, Hyungon ; Cho, Hansu ; Lee, Seungwook ; Kang, Brent Byunghoon ; Paek, Yunheung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 48~59
DOI : 10.5573/JSTS.2015.15.1.048
In recent years, there are increasing threats of rootkits that undermine the integrity of a system by manipulating OS kernel. To cope with the rootkits, in Vigilare, the snoop-based monitoring which snoops the memory traffics of the host system was proposed. Although the previous work shows its detection capability and negligible performance loss, the problem is that the proposed design is not acceptable in recent commodity mobile application processors (APs) which have become de facto the standard computing platforms of smart devices. To mend this problem and adopt the idea of snoop-based monitoring in commercial products, in this paper, we propose a snoop-based monitor design called S-Mon, which is designed for the AP platforms. In designing S-Mon, we especially consider two design constraints in the APs which were not addressed in Vigilare; the unified memory model and the crossbar switch interconnect. Taking into account those, we derive a more realistic architecture for the snoop-based monitoring and a new hardware module, called the region controller, is also proposed. In our experiments on a simulation framework modeling a productionquality device, it is shown that our S-Mon can detect the rootkit attacks while the runtime overhead is also negligible.
Color Image Enhancement Based on Adaptive Nonlinear Curves of Luminance Features
Cho, Hosang ; Kim, Geun-Jun ; Jang, Kyounghoon ; Lee, Sungmok ; Kang, Bongsoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 60~67
DOI : 10.5573/JSTS.2015.15.1.060
This paper proposes an image-dependent color image enhancement method that uses adaptive luminance enhancement and color emphasis. It effectively enhances details of low-light regions while maintaining well-balanced luminance and color information. To compare the structure similarity and naturalness, we used the tone mapped image quality index (TMQI). The proposed method maintained better structure similarity in the enhanced image than did the space-variant luminance map (SVLM) method or the adaptive and integrated neighborhood dependent approach for nonlinear enhancement (AINDANE). The proposed method required the smallest computation time among the three algorithms. The proposed method can be easily implemented using the field-programmable gate array (FPGA), with low hardware resources and with better performance in terms of similarity.
LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices
Yoo, Seunghoon ; Lee, Eunji ; Bahn, Hyokyung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 68~76
DOI : 10.5573/JSTS.2015.15.1.068
Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.
Design of Low-Power and Low-Latency 256-Radix Crossbar Switch Using Hyper-X Network Topology
Baek, Seung-Heon ; Jung, Sung-Youb ; Kim, Jaeha ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 77~84
DOI : 10.5573/JSTS.2015.15.1.077
This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of
. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of
Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs
Ansari, M. Adil ; Kim, Dooyoung ; Jung, Jihun ; Park, Sungju ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 85~95
DOI : 10.5573/JSTS.2015.15.1.085
Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.
Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links
Lim, Hyun-Wook ; Kong, Bai-Sun ; Jun, Young-Hyun ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 96~100
DOI : 10.5573/JSTS.2015.15.1.096
Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a
ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at
BER increased from 0.261 UI to 0.363 UI with stable loop convergence.
Enhanced-Precision LHSMC of Electrical Circuit Considering Low Discrepancy
Park, Eun-Suk ; Oh, Deok-Keun ; Kim, Ju-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 101~113
DOI : 10.5573/JSTS.2015.15.1.101
The Monte-Carlo (MC) technique is very efficient solution for statistical problem. Various MC methods can easily be applied to statistical circuit performance analysis. Recently, as the number of process parameters and their impact, has increasingly affected circuit performance, a sufficient sample size is required in order to consider high dimensionality, profound nonlinearity, and stringent accuracy requirements. Also, it is important to identify the performance of circuit as soon as possible. In this paper, Fast MC method is proposed for efficient analysis of circuit performance. The proposed method analyzes performance using enhanced-precision Latin Hypercube Sampling Monte Carlo (LHSMC). To increase the accuracy of the analysis, we calculate the effective dimension for the low discrepancy value on critical parameters. This will guarantee a robust input vector for the critical parameters. Using a 90nm process parameter and OP-AMP, we verified the accuracy and reliability of the proposed method in comparison with the standard MC, LHS and Quasi Monte Carlo (QMC).
Effects of Current Spreading in GaN-based Light-emitting Diodes Using ITO Spreading Pad
Kim, Jang Hyun ; Kim, Garam ; Park, Euyhwan ; Kang, Dong Hoon ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 114~121
DOI : 10.5573/JSTS.2015.15.1.114
In conventional LEDs, a mesa-structure is usually used and it causes the current to be overcrowded in a specific region. We propose a novel structure of GaN-based LED to overcome this problem. In order to distribute the current in an active region, a spreading pad is inserted at the p-type region in the GaN based LED device. The inserted spreading pad helps the current flow because it is more conductive than the p-type GaN layer. By performing electrical and optical simulations, the effects of the spreading pad insertion are confirmed. The results of electrical simulation show that the current spreads more uniformly and more radiative recombination is produced as well. Moreover, from the optical simulation, it is revealed that the ITO is less absorptive material than p-GaN if the condition of specific wavelength sources is satisfied. Considering all of the results, we can conclude that the luminescent power is enhanced by the spreading pad.
A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS
Lee, Juri ; Park, Hyung Gu ; Kim, In Seong ; Pu, YoungGun ; Hwang, Keum Cheol ; Yang, Youngoo ; Lee, Kang-Yoon ; Seo, Munkyo ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 122~130
DOI : 10.5573/JSTS.2015.15.1.122
This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in
complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum
gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is
for 4-channel. The power dissipation is 47.64 mW/1ch.
Investigation of Hetero - Material - Gate in CNTFETs for Ultra Low Power Circuits
Wang, Wei ; Xu, Min ; Liu, Jichao ; Li, Na ; Zhang, Ting ; Jiang, Sitao ; Zhang, Lu ; Wang, Huan ; Gao, Jian ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 131~144
DOI : 10.5573/JSTS.2015.15.1.131
An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of
have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.
A Reconfigurable Lighting Engine for Mobile GPU Shaders
Ahn, Jonghun ; Choi, Seongrim ; Nam, Byeong-Gyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 145~149
DOI : 10.5573/JSTS.2015.15.1.145
A reconfigurable lighting engine for widely used lighting models is proposed for low-power GPU shaders. Conventionally, lighting operations that involve many complex arithmetic operations were calculated by the shader programs on the GPU, which led to a significant energy overhead. In this letter, we propose a lighting engine to improve the energy-efficiency by supporting the widely used advanced lighting models in hardware. It supports the Blinn-Phong, Oren-Nayar, and Cook-Torrance models, by exploiting the logarithmic arithmetic and optimizing the trigonometric function evaluations for the energy-efficiency. Experimental results demonstrate 12.7%, 42.5%, and 35.5% reductions in terms of power-delay product from the shader program implementations for each lighting model. Moreover, our work shows 10.1% higher energy-efficiency for the Blinn-Phong model compared to the prior art.
An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures
Hwang, Jaemin ; Choi, Seongrim ; Nam, Byeong-Gyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 1, 2015, Pages 150~153
DOI : 10.5573/JSTS.2015.15.1.150
An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.