Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 15, Issue 6 - Dec 2015
Volume 15, Issue 5 - Oct 2015
Volume 15, Issue 4 - Aug 2015
Volume 15, Issue 3 - Jun 2015
Volume 15, Issue 2 - Apr 2015
Volume 15, Issue 1 - Feb 2015
Selecting the target year
An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement
Kim, Jong-Hoon ; Lim, Ji-Hoon ; Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 155~167
DOI : 10.5573/JSTS.2015.15.2.155
An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a
process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.
Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM
Cai, Shuo ; Kuang, Ji-Shun ; Liu, Tie-Qiao ; Wang, Wei-Zheng ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 168~176
DOI : 10.5573/JSTS.2015.15.2.168
Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.
A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit
Yoon, Myungchul ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 177~183
DOI : 10.5573/JSTS.2015.15.2.177
A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with
process technology in finding a winner among 1024 of 16-bit data.
Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement
Lee, Sooeun ; Han, Seungho ; Lee, Ikho ; Sim, Jae-Yoon ; Park, Hong-June ; Kim, Byungsub ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 184~193
DOI : 10.5573/JSTS.2015.15.2.184
This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method.
A Low-Power Low-Complexity Transmitter for FM-UWB Systems
Zhou, Bo ; Wang, Jingchao ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 194~201
DOI : 10.5573/JSTS.2015.15.2.194
A frequency modulated ultra-wideband (FM-UWB) transmitter with a high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM is proposed, featuring low power and low complexity. A prototype 3.65-4.25 GHz FM-UWB transceiver employing the presented transmitter is fabricated in
CMOS for short-range wireless data transmission. Experimental results show a bit error rate (BER) of
at a data rate of 12.5 kb/s with a communication distance of 60 cm is achieved and the power dissipation of 4.3 mW for the proposed transmitter is observed from a 1.8 V supply.
High-Robust Relaxation Oscillator with Frequency Synthesis Feature for FM-UWB Transmitters
Zhou, Bo ; Wang, Jingchao ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 202~207
DOI : 10.5573/JSTS.2015.15.2.202
A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in
CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.
Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains
Song, Sung-Gun ; Park, Seong-Mo ; Lee, Jeong-Gun ; Oh, Myeong-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 208~222
DOI : 10.5573/JSTS.2015.15.2.208
For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered
CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.
Characterizing Memory References for Smartphone Applications and Its Implications
Lee, Soyoon ; Bahn, Hyokyung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 223~231
DOI : 10.5573/JSTS.2015.15.2.223
As smartphones support a variety of applications and their memory demand keeps increasing, the design of an efficient memory management policy is becoming increasingly important. Meanwhile, as nonvolatile memory (NVM) technologies such as PCM and STT-MRAM have emerged as new memory media of smartphones, characterizing memory references for NVM-based smartphone memory systems is needed. For the deep understanding of memory access features in smartphones, this paper performs comprehensive analysis of memory references for various smartphone applications. We first analyze the temporal locality and frequency of memory reference behaviors to quantify the effects of the two properties with respect to the re-reference likelihood of pages. We also analyze the skewed popularity of memory references and model it as a Zipf-like distribution. We expect that the result of this study will be a good guidance to design an efficient memory management policy for future smartphones.
Influence of the Recombination Parameters at the Si/SiO
Interface on the Ideality of the Dark Current of High Efficiency Silicon Solar Cells
Kamal, Husain ; Ghannam, Moustafa ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 232~242
DOI : 10.5573/JSTS.2015.15.2.232
Analytical study of surface recombination at the
interface is carried out in order to set the optimum surface conditions that result in minimum dark base current and maximum open circuit voltage in silicon solar cells. Recombination centers are assumed to form a continuum rather than to be at a single energy level in the energy gap. It is shown that the presence of a hump in the dark I-V characteristics of high efficiency PERL cells is due to the dark current transition from a high surface recombination regime at low voltage to a low surface recombination regime at high voltage. Successful fitting of reported dark I-V characteristics of a typical PERL cell is obtained with several possible combinations of surface parameters including equal electron and hole capture cross sections.
Dark Conductivity in Semi-Insulating Crystals of CdTe:Sn
Makhniy, V.P. ; Sklyarchuk, V.M. ; Vorobiev, Yu.V. ; Horley, P.P. ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 243~248
DOI : 10.5573/JSTS.2015.15.2.243
We prepared semi-insulating CdTe for radiation detectors by isothermal annealing of single crystals grown by Bridgeman technique in a sealed quartz container filled with Sn vapor. The resistivity of CdTe:Sn samples thus obtained was of order of
at room temperature with electrons lifetime of
s, which is appropriate for the applications desired. Analysis of electric transport characteristics depending on temperature, sample thickness and voltage applied revealed the presence of traps with concentration of about
with the corresponding energy level at 0.8 - 0.9 eV counted from the bottom of conduction band. The conductivity was determined by electron injection from electrodes in space charge limited current mode.
Improvement of Device Characteristic on Solution-Processed InGaZnO Thin-Film-Transistor (TFTs) using Microwave Irradiation
Moon, Sung-Wan ; Cho, Won-Ju ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 249~254
DOI : 10.5573/JSTS.2015.15.2.249
Solution-derived amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistor (TFTs) were developed using a microwave irradiation treatment at low process temperature below
. Compared to conventional furnace-annealing, the a-IGZO TFTs annealed by microwave irradiation exhibited better electrical characteristics in terms of field effect mobility, SS, and on/off current ratio, although the annealing temperature of microwave irradiation is much lower than that of furnace annealing. The microwave irradiated TFTs showed a smaller
shift under the positive gate bias stress (PGBS) and negative gate bias stress (NGBS) tests owing to a lower ratio of oxygen vacancies, surface absorbed oxygen molecules, and reduced interface trapping in a-IGZO. Therefore, microwave irradiation is very promising to low-temperature process.
Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas
Jang, Soohyun ; Lee, Seongjoo ; Jung, Yunho ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 255~266
DOI : 10.5573/JSTS.2015.15.2.255
In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately
with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.
A Study on the Band Structure of ZnO/CdS Heterojunction for CIGS Solar-Cell Application
Sim, Hana ; Lee, Jeongmin ; Cho, Seongjae ; Cho, Eou-Sik ; Kwon, Sang Jik ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 267~275
DOI : 10.5573/JSTS.2015.15.2.267
In this paper, ZnO films were prepared by atomic layer deposition (ALD) and CdS films were deposited using chemical bath deposition (CBD) to form ZnO/CdS heterojunction. More accurate mapping of band arrangement of the ZnO/CdS heterojunction has been performed by analyzing its electrical and optical characteristics in depth by various methods including transmittance, x-ray photoemission spectroscopy (XPS), and ultraviolet photoemission spectroscopy (UPS). The optical bandgap energies (
) of ZnO and CdS were 3.27 eV and 2.34 eV, respectively. UPS was capable of extracting the ionization potential energies (IPEs) of the materials, which turned out to be 8.69 eV and 7.30 eV, respectively. The electron affinity (EA) values of ZnO and CdS calculated from IPE and
were 5.42 eV and 4.96 eV, respectively. Energy-band structures of the heterojunction could be accurately drawn from these parameters taking the conduction band offset (CBO) into account, which will substantially help acquisition of the full band structures of the thin films in the CIGS solar-cell device and contribute to the optimal device designs.
D-band Stacked Amplifiers based on SiGe BiCMOS Technology
Yun, Jongwon ; Kim, Hyunchul ; Song, Kiryong ; Rieh, Jae-Sung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 276~279
DOI : 10.5573/JSTS.2015.15.2.276
This paper presents two 3-stage D-band stacked amplifiers developed in a
SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.
A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications
Lee, Ockgoo ; Ryu, Hyunsik ; Baek, Seungjun ; Nam, Ilku ; Jeong, Minsu ; Kim, Bo-Eun ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 280~285
DOI : 10.5573/JSTS.2015.15.2.280
A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.
Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage
Kwon, Wookhyun ; Park, In Jun ; Shin, Changhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 286~291
DOI : 10.5573/JSTS.2015.15.2.286
For highly scalable NAND flash memory applications, a compact (
) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.
Wide-Input Range Dual Mode PWM / Linear Buck Converter with High robustness ESD Protection Circuit
Song, Bo-Bae ; Koo, Yong-Seo ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 292~300
DOI : 10.5573/JSTS.2015.15.2.292
This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between
, the converter has variations in temperature of
in the PWM mode and of
in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.
An Wideband GaN Low Noise Amplifier in a 3×3 mm
Quad Flat Non-leaded Package
Park, Hyun-Woo ; Ham, Sun-Jun ; Lai, Ngoc-Duy-Hien ; Kim, Nam-Yoon ; Kim, Chang-Woo ; Yoon, Sang-Woong ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 301~306
DOI : 10.5573/JSTS.2015.15.2.301
An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a
GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the
QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses (
) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is
. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.
Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture
Kim, Yoonjin ; Sohn, Seungyeon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 307~311
DOI : 10.5573/JSTS.2015.15.2.307
In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).
Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology
Jang, Seong-Yong ; Kwon, Sung-Kyu ; Shin, Jong-Kwan ; Yu, Jae-Nam ; Oh, Sun-Ho ; Jeong, Jin-Woong ; Song, Hyeong-Sub ; Kim, Choul-Young ; Lee, Ga-Won ; Lee, Hi-Deok ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 2, 2015, Pages 312~317
DOI : 10.5573/JSTS.2015.15.2.312
In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source (
) and gate-to-drain (
) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency (
) and maximum-oscillation frequency (
) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.