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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 15, Issue 6 - Dec 2015
Volume 15, Issue 5 - Oct 2015
Volume 15, Issue 4 - Aug 2015
Volume 15, Issue 3 - Jun 2015
Volume 15, Issue 2 - Apr 2015
Volume 15, Issue 1 - Feb 2015
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A Piezoelectric Energy Harvester with High Efficiency and Low Circuit Complexity
Do, Xuan-Dien ; Nguyen, Huy-Hieu ; Han, Seok-Kyun ; Ha, Dong Sam ; Lee, Sang-Gug ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 319~325
DOI : 10.5573/JSTS.2015.15.3.319
This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in
CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 326~333
DOI : 10.5573/JSTS.2015.15.3.326
This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in
CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.
The Design of a 0.15 ps High Resolution Time-to-Digital Converter
Lee, Jongsuk ; Moon, Yong ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 334~341
DOI : 10.5573/JSTS.2015.15.3.334
This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a
CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.
An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL
Lee, Jong Mi ; Jee, Dong-Woo ; Kim, Byungsub ; Park, Hong-June ; Sim, Jae-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 342~348
DOI : 10.5573/JSTS.2015.15.3.342
This paper presents a 1.9-GHz digital
fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in
CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.
A Fully-Differential Correlated Doubling Sampling Readout Circuit for Mutual-capacitance Touch Screens
Kwon, Kihyun ; Kim, Sung-Woo ; Bien, Franklin ; Kim, Jae Joon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 349~355
DOI : 10.5573/JSTS.2015.15.3.349
A fully-differential touch-screen sensing architecture is presented to improve noise immunity and also support most multi-touch events minimizing the number of amplifiers and their silicon area. A correlated double sampling function is incorporated to reduce DC offset and low-frequency noises, and a stabilizer circuit is also embedded to minimize inherent transient fluctuations. A prototype of the proposed readout circuit was fabricated in a
CMOS process and its differential operation in response to various touch events was experimentally verified. With a 3.3 V supply, the current dissipation was 3.4 mA at normal operation and
in standby mode.
Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling
Li, Chunquan ; Zou, Meng-Qiang ; Shang, Yuling ; Zhang, Ming ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 356~364
DOI : 10.5573/JSTS.2015.15.3.356
The transmission performance of TSV considering the effect of electronic-thermal coupling is an new challenge in three dimension integrated circuit. This paper presents the thermal equivalent circuit (TEC) model of the TSV, and discussed the thermal equivalent parameters for TSV. Si layer is equivalent to transmission line according to its thermal characteristic. Thermal transient response (TTR) of TSV considering electronic-thermal coupling effects are proposed, iteration flow electronic-thermal coupling for TSV is analyzed. Furthermore, the influences of TTR are investigated with the non-coupling and considering coupling for TSV. Finally, the relationship among temperature, thickness of
, radius of via and frequency of excitation source are addressed, which are verified by the simulation.
Neuron Circuit Using a Thyristor and Inter-neuron Connection with Synaptic Devices
Ranjan, Rajeev ; Kwon, Min-Woo ; Park, Jungjin ; Kim, Hyungjin ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 365~373
DOI : 10.5573/JSTS.2015.15.3.365
We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synaptic-neuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.
Worst Case Sampling Method with Confidence Ellipse for Estimating the Impact of Random Variation on Static Random Access Memory (SRAM)
Oh, Sangheon ; Jo, Jaesung ; Lee, Hyunjae ; Lee, Gyo Sub ; Park, Jung-Dong ; Shin, Changhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 374~380
DOI : 10.5573/JSTS.2015.15.3.374
As semiconductor devices are being scaled down, random variation becomes a critical issue, especially in the case of static random access memory (SRAM). Thus, there is an urgent need for statistical methodologies to analyze the impact of random variations on the SRAM. In this paper, we propose a novel sampling method based on the concept of a confidence ellipse. Results show that the proposed method estimates the SRAM margin metrics in high-sigma regimes more efficiently than the standard Monte Carlo (MC) method.
A 85-mW Multistandard Multiband CMOS Mobile TV Tuner for DVB-H/T, T-DMB, and ISDB-T Applications with FM Reception
Nam, Ilku ; Bae, Jong-Dae ; Moon, Hyunwon ; Park, Byeong-Ha ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 381~389
DOI : 10.5573/JSTS.2015.15.3.381
A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a
CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator.
A Direct AC Driver with Reduced Flicker for Multiple String LEDs
Kim, Junsik ; Park, Shihong ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 390~396
DOI : 10.5573/JSTS.2015.15.3.390
This paper proposes a method to reduce flicker when running an AC-power direct-drive type multiple string LED driver IC. The proposed method greatly decreases flicker using one capacitor and P-type MOSFET transistor (PMOS). The flicker index (FI) was reduced by over 40% through experiments, and less than half of the conventional external components are used in the passive valley fill circuit, which gives an advantage in the cost and utilization in the design of LED lighting modules. The 0.35 um 700 V BCD process was used to manufacture this LED driver.
SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment
Wang, Weizheng ; Cai, Shuo ; Xiang, Lingyun ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 397~403
DOI : 10.5573/JSTS.2015.15.3.397
This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.
An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors
Kwon, Hye-Jung ; Lim, Ji-Hoon ; Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 404~416
DOI : 10.5573/JSTS.2015.15.3.404
Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.
A 6.5 - 8.5 GHz CMOS UWB Transmitter Using Switched LC VCO
Eo, Yun Seong ; Park, Myung Cheol ; Ha, Min-Cheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 417~422
DOI : 10.5573/JSTS.2015.15.3.417
A 6.5 - 8.5 GHz CMOS UWB transmitter is implemented using
CMOS technology. The transmitter is mainly composed of switched LC VCO and digital pulse generator (DPG). Using RF switch and DPG, the uniform power and sidelobe rejection are achieved irrespective of the carrier frequency. The measured UWB carrier frequency range is 7 ~ 8 GHz and the pulse width is tunable from 1 to 2 ns. The measured energy efficiency per pulse is 2.1 % and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier. The chip core size is
Multi-operation-based Constrained Random Verification for On-Chip Memory
Son, Hyeonuk ; Jang, Jaewon ; Kim, Heetae ; Kang, Sungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 423~426
DOI : 10.5573/JSTS.2015.15.3.423
Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.
High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme
Kim, Cheolho ; Yun, Haram ; Ajaz, Sabooh ; Lee, Hanho ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 3, 2015, Pages 427~435
DOI : 10.5573/JSTS.2015.15.3.427
This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.