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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 15, Issue 6 - Dec 2015
Volume 15, Issue 5 - Oct 2015
Volume 15, Issue 4 - Aug 2015
Volume 15, Issue 3 - Jun 2015
Volume 15, Issue 2 - Apr 2015
Volume 15, Issue 1 - Feb 2015
Selecting the target year
Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation
Vanitha, P. ; Balamurugan, N.B. ; Priya, G. Lakshmi ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 585~593
DOI : 10.5573/JSTS.2015.15.6.585
In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.
A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks
Jin, Xuefan ; Bae, Jun-Han ; Chun, Jung-Hoon ; Kim, Jintae ; Kwon, Kee-Won ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 594~600
DOI : 10.5573/JSTS.2015.15.6.594
A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from
with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies
of the output clock are 1.91 ps and 18 ps, respectively.
Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process
Wang, Yang ; Jin, Xiangliang ; Zhou, Acheng ; Yang, Liu ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 601~607
DOI : 10.5573/JSTS.2015.15.6.601
A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (
) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard
24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.
Multi-Channel Audio CODEC with Channel Interference Suppression
Choi, Moo-Yeol ; Lee, Sung-No ; Lee, Myung-Jin ; Lee, Yong-Hee ; Park, Ho-Jin ; Kong, Bai-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 608~614
DOI : 10.5573/JSTS.2015.15.6.608
A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.
Dynamic Redundancy-based Fault-Recovery Scheme for Reliable CGRA-based Multi-Core Architecture
Kim, Yoonjin ; Sohn, Seungyeon ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 615~628
DOI : 10.5573/JSTS.2015.15.6.615
CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).
Current-Steered Active Balun with Phase Correction
Park, Ji An ; Jin, Ho Jeong ; Cho, Choon Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 629~633
DOI : 10.5573/JSTS.2015.15.6.629
An active balun using current steering for phase correction is presented. The proposed active balun is constructed with two different unit balun structures based on current steering to reduce phase and amplitude errors. This type of topology can be compared with the conventional phase and amplitude correction techniques which do not incorporate the current steering. Designed and fabricated active balun in
CMOS process operates over 0.95 - 1.45 GHz band, showing input reflection coefficient under -15 dB, phase error of
and gain error of 0.5 dB. Gain is measured to be 0.3 dB maximum and power consumption of 7.2 mW is measured.
Scalable Application Mapping for SIMD Reconfigurable Architecture
Kim, Yongjoo ; Lee, Jongeun ; Lee, Jinyong ; Paek, Yunheung ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 634~646
DOI : 10.5573/JSTS.2015.15.6.634
Coarse-Grained Reconfigurable Architecture (CGRA) is a very promising platform that provides fast turn-around-time as well as very high energy efficiency for multimedia applications. One of the problems with CGRAs, however, is application mapping, which currently does not scale well with geometrically increasing numbers of cores. To mitigate the scalability problem, this paper discusses how to use the SIMD (Single Instruction Multiple Data) paradigm for CGRAs. While the idea of SIMD is not new, SIMD can complicate the mapping problem by adding an additional dimension of iteration mapping to the already complex problem of operation and data mapping, which are all interdependent, and can thus significantly affect performance through memory bank conflicts. In this paper, based on a new architecture called SIMD reconfigurable architecture, which allows SIMD execution at multiple levels of granularity, we present how to minimize bank conflicts considering all three related sub-problems, for various RA organizations. We also present data tiling and evaluate a conflict-free scheduling algorithm as a way to eliminate bank conflicts for a certain class of mapping problem.
Pull-In Voltage Modeling of Graphene Formed Nickel Nano Electro Mechanical Systems (NEMS)
Lim, Songnam ; Lee, Jong-Ho ; Choi, Woo Young ; Cho, Il Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 647~652
DOI : 10.5573/JSTS.2015.15.6.647
Pull-in voltage model of nano-electro-mechanical system with graphene is investigated for the device optimization. In the pull in voltage model, thickness of graphene layer is assumed to be uniform in vertical and lateral direction. Finite element analysis simulation has verified the feasibility of the suggested model. From the suggested model, pull-in voltage change with graphene thickness and cantilever length can be estimated. Maximum induced stress and graphene thickness have a reciprocal relationship.
Accurate RF C-V Method to Extract Effective Channel Length and Parasitic Capacitance of Deep-Submicron LDD MOSFETs
Lee, Sangjun ; Lee, Seonghearn ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 653~657
DOI : 10.5573/JSTS.2015.15.6.653
A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.
Integrate-and-Fire Neuron Circuit and Synaptic Device using Floating Body MOSFET with Spike Timing-Dependent Plasticity
Kwon, Min-Woo ; Kim, Hyungjin ; Park, Jungjin ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 658~663
DOI : 10.5573/JSTS.2015.15.6.658
In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.
Overstress-Free 4 × VDD Switch in a Generic Logic Process Supporting High and Low Voltage Modes
Song, Seung-Hwan ; Kim, Jongyeon ; Kim, Chris H. ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 664~670
DOI : 10.5573/JSTS.2015.15.6.664
A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to
. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.
The Oscillation Frequency of CML-based Multipath Ring Oscillators
Song, Sanquan ; Kim, Byungsub ; Xiong, Wei ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 671~677
DOI : 10.5573/JSTS.2015.15.6.671
A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor
, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor
an attractive option for lower power applications.
Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation
Li, Chang-Lin ; Kim, Hyun Joong ; Heo, Seo Weon ; Han, Tae Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 678~684
DOI : 10.5573/JSTS.2015.15.6.678
Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.
Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array
Shin, SangHak ; Byeon, Sang-Don ; Song, Jeasang ; Truong, Son Ngoc ; Mo, Hyun-Sun ; Kim, Deajeong ; Min, Kyeong-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 685~694
DOI : 10.5573/JSTS.2015.15.6.685
In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of
, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of
, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.
A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator
Lee, Han-Yeol ; Jeong, Dong-Gil ; Hwang, Yu-Jeong ; Lee, Hyun-Bae ; Jang, Young-Chan ;
JSTS:Journal of Semiconductor Technology and Science, volume 15, issue 6, 2015, Pages 695~702
DOI : 10.5573/JSTS.2015.15.6.695
A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and