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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
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Volume & Issues
Volume 16, Issue 4 - Aug 2016
Volume 16, Issue 3 - Jun 2016
Volume 16, Issue 2 - Apr 2016
Volume 16, Issue 1 - Feb 2016
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Design of a Two-Stage Driver for LED MR16 Retrofit Lamps Compatible with Electronic Transformers
Yim, Sungwon ; Lee, Hyongmin ; Lee, Bongjin ; Kang, Kyucheol ; Kim, Suhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 1~10
DOI : 10.5573/JSTS.2016.16.1.001
Drivers for LED MR16 retrofit lamps need to be compatible with the dimmers and electronic transformers which originally operated with the halogen lamps to be replaced. We present a two-stage MR16 LED driver consisting of a boost converter in the first stage and a buck converter in the second stage. Our design has been analyzed in the frequency domain using simulations to demonstrate that it effectively suppresses the high-frequency components of the AC output of the electronic transformer. Experiment results with a driver prototype verify the simulation results as well as dimmability.
Post-Silicon Tuning Based on Flexible Flip-Flop Timing
Seo, Hyungjung ; Heo, Jeongwoo ; Kim, Taewhan ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 11~22
DOI : 10.5573/JSTS.2016.16.1.011
Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (
) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.
Low-Power Write-Circuit with Status-Detection for STT-MRAM
Shin, Kwang-Seob ; Im, Saemin ; Park, Sang-Gyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 23~30
DOI : 10.5573/JSTS.2016.16.1.023
We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in write-circuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a
Novel Self-Reference Sense Amplifier for Spin-Transfer-Torque Magneto-Resistive Random Access Memory
Choi, Jun-Tae ; Kil, Gyu-Hyun ; Kim, Kyu-Beom ; Song, Yun-Heub ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 31~38
DOI : 10.5573/JSTS.2016.16.1.031
A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard
CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.
Enhanced Efficiency of Transmit and Receive Module with Ga Doped MgZnO Semiconductor Device by Growth Thickness
Shim, Bo-Hyun ; Jo, Hee-Jin ; Kim, Dong-Jin ; Chae, Jong-Mok ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 39~43
DOI : 10.5573/JSTS.2016.16.1.039
The structural, electrical properties of Ga doped MgZnO transparent conductive oxide (TCO) films by ratio-frequency(RF) magnetron sputtering were investigated. Ga doped MgZnO TCO films were deposited on the sapphire substrates at
varying growth thickness 200 to 600 nm. The optical properties of Ga doped MgZnO TCO films were showed above 85% transmittance from 300 to 1000 nm region. In addition, the current density (
(CIGS) solar cells was improved by using the MgZnO:Ga films of 500 nm thickness because of outstanding electrical properties. The
solar cells with MgZnO:Ga transparent conducing layer yielded an efficiency of 9.8% with current density (
), open circuit voltage (540.2 V) and fill factor (62.2) under AM 1.5 illumination.
Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT
Kim, Jong-hak ; Kim, Jae-gon ; Oh, Jung-kyun ; Kang, Seong-muk ; Cho, Jun-Dong ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 44~57
DOI : 10.5573/JSTS.2016.16.1.044
Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.
Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor
Angamuthu, Rathinam ; Thangavelu, Karthikeyan ; Kannan, Ramani ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 58~69
DOI : 10.5573/JSTS.2016.16.1.058
This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.
Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors
Park, Jun-Sang ; Jeong, Jong-Min ; An, Tai-Ji ; Ahn, Gil-Cho ; Lee, Seung-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 70~79
DOI : 10.5573/JSTS.2016.16.1.070
This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a
CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of
consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.
A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache
Kong, Joonho ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 80~90
DOI : 10.5573/JSTS.2016.16.1.080
Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.
Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications
Wang, Wei ; Xu, Hongsong ; Huang, Zhicheng ; Zhang, Lu ; Wang, Huan ; Jiang, Sitao ; Xu, Min ; Gao, Jian ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 91~105
DOI : 10.5573/JSTS.2016.16.1.091
Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of
have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.
Modeling of Electrolyte Thermal Noise in Electrolyte-Oxide-Semiconductor Field-Effect Transistors
Park, Chan Hyeong ; Chung, In-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 106~111
DOI : 10.5573/JSTS.2016.16.1.106
Thermal noise generated in the electrolyte is modeled for the electrolyte-oxide-semiconductor field-effect transistors. Two noise sources contribute to output noise currents. One is the thermal noise generated in the bulk electrolyte region, and the other is the thermal noise from the double-layer region at the electrolyte-oxide interface. By employing two slightly-different equivalent circuits for two noise current sources, the power spectral density of output noise current is calculated. From the modeling and simulated results, the bulk electrolyte thermal noise dominates the double-layer thermal noise. Electrolyte thermal noise are computed for three different concentrations of NaCl electrolyte. The derived formulas give a good agreement with the published experimental data.
Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels
Park, Hwan-Wook ; Lim, Hyun-Wook ; Kong, Bai-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 112~117
DOI : 10.5573/JSTS.2016.16.1.112
This paper presents a half-rate current-integrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at
Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor
Nguyen, Tuy Tan ; Lee, Hanho ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 118~125
DOI : 10.5573/JSTS.2016.16.1.118
This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.
Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application
Lee, DongSoo ; Lee, Juri ; Park, Hyung-Gu ; Choi, JinWook ; Park, SangHyeon ; Kim, InSeong ; Pu, YoungGun ; Kim, JaeYoung ; Hwang, Keum Cheol ; Yang, Youngoo ; Seo, Munkyo ; Lee, Kang-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 126~142
DOI : 10.5573/JSTS.2016.16.1.126
This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal
matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in
, 1-poly, 6-metal CMOS technology. The die area of the transceiver is
. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
Han, Sangwoo ; Lim, Jongtae ; Kim, Jongsun ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 1, 2016, Pages 143~146
DOI : 10.5573/JSTS.2016.16.1.143
A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just
. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.