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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 16, Issue 4 - Aug 2016
Volume 16, Issue 3 - Jun 2016
Volume 16, Issue 2 - Apr 2016
Volume 16, Issue 1 - Feb 2016
Selecting the target year
Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device
Kim, Sungjun ; Cho, Seongjae ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 147~152
DOI : 10.5573/JSTS.2016.16.2.147
In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having
Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.
Characterization of Stiffness Coefficients of Silicon Versus Temperature using "Poisson's Rati" Measurements
Cho, Chun-Hyung ; Cha, Ho-Young ; Sung, Hyuk-Kee ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 153~158
DOI : 10.5573/JSTS.2016.16.2.153
The elastic material constants, stiffness constants (
), are three unique coefficients that establish the relation between stress and strain. Accurate knowledge of mechanical properties and the stiffness coefficients for silicon is required for design of Micro-Electro-Mechanical Systems (MEMS) devices for proper modeling of stress and strain in electronic packaging. In this work, the stiffness coefficients for silicon as a function of temperature from
have been extracted by using the experimental measurements of Poisson's ratio (
) of silicon in several directions.
High-Speed Low-Power Junctionless Field-Effect Transistor with Ultra-Thin Poly-Si Channel for Sub-10-nm Technology Node
Kim, Youngmin ; Lee, Junsoo ; Cho, Yongbeom ; Lee, Won Jae ; Cho, Seongjae ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 159~165
DOI : 10.5573/JSTS.2016.16.2.159
Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.
Edge Cut Process for Reducing Ni Content at Channel Edge Region in Metal Induced Lateral Crystallization Poly-Si TFTs
SEOK, Ki Hwan ; Kim, Hyung Yoon ; Park, Jae Hyo ; Lee, Sol Kyu ; Lee, Yong Hee ; Joo, Seung Ki ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 166~171
DOI : 10.5573/JSTS.2016.16.2.166
Nickel silicide is main issue in Polycrystalline silicon Thin Film Transistor (TFT) which is made by Metal Induced Lateral Crystallization (MILC) method. This Nickel silicide acts as a defect center, and this defect is one of the biggest reason of the high leakage current. In this research, we fabricated polycrystalline TFTs with novel method called Edge Cut (EC). With this new fabrication method, we assumed that nickel silicide at the edge of the channel region is reduced. Electrical properties are measured and trap state density also calculated using Levinson & Proano method.
Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications
Yoon, Young Jun ; Seo, Jae Hwa ; Cho, Seongjae ; Kwon, Hyuck-In ; Lee, Jung-Hee ; Kang, In Man ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 172~178
DOI : 10.5573/JSTS.2016.16.2.172
In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length (
) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current (
. In addition, the use of the highk spacer dielectric
improves the on-state current (
) with an intrinsic delay time (
) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower
at a lower supply voltage (
) of 0.2 V.
Contact Resistance and Leakage Current of GaN Devices with Annealed Ti/Al/Mo/Au Ohmic Contacts
Ha, Min-Woo ; Choi, Kangmin ; Jo, Yoo Jin ; Jin, Hyun Soo ; Park, Tae Joo ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 179~184
DOI : 10.5573/JSTS.2016.16.2.179
In recent years, the on-resistance, power loss and cell density of Si power devices have not exhibited significant improvements, and performance is approaching the material limits. GaN is considered an attractive material for future high-power applications because of the wide band-gap, large breakdown field, high electron mobility, high switching speed and low on-resistance. Here we report on the Ohmic contact resistance and reverse-bias characteristics of AlGaN/GaN Schottky barrier diodes with and without annealing. Annealing in oxygen at
resulted in an increase in the breakdown voltage from 641 to 1,172 V for devices with an anode-cathode separation of
. However, these annealing conditions also resulted in an increase in the contact resistance of
, which is attributed to oxidation of the metal contacts. Auger electron spectroscopy revealed diffusion of oxygen and Au into the AlGaN and GaN layers following annealing. The improved reverse-bias characteristics following annealing in oxygen are attributed to passivation of dangling bonds and plasma damage due to interactions between oxygen and GaN/AlGaN. Thermal annealing is therefore useful during the fabrication of high-voltage GaN devices, but the effects on the Ohmic contact resistance should be considered.
Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor
Lee, Hyunseul ; Cho, Karam ; Shin, Changhwan ; Shin, Hyungcheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 185~190
DOI : 10.5573/JSTS.2016.16.2.185
nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (
) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the
shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.
3D TCAD Analysis of Hot-Carrier Degradation Mechanisms in 10 nm Node Input/Output Bulk FinFETs
Son, Dokyun ; Jeon, Sangbin ; Kang, Myounggon ; Shin, Hyungcheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 191~197
DOI : 10.5573/JSTS.2016.16.2.191
In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.
Effects of Mg Suppressor Layer on the InZnSnO Thin-Film Transistors
Song, Chang-Woo ; Kim, Kyung-Hyun ; Yang, Ji-Woong ; Kim, Dae-Hwan ; Choi, Yong-Jin ; Hong, Chan-Hwa ; Shin, Jae-Heon ; Kwon, Hyuck-In ; Song, Sang-Hun ; Cheong, Woo-Seok ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 198~203
DOI : 10.5573/JSTS.2016.16.2.198
We investigate the effects of magnesium (Mg) suppressor layer on the electrical performances and stabilities of amorphous indium-zinc-tin-oxide (a-ITZO) thin-film transistors (TFTs). Compared to the ITZO TFT without a Mg suppressor layer, the ITZO:Mg TFT exhibits slightly smaller field-effect mobility and much reduced subthreshold slope. The ITZO:Mg TFT shows improved electrical stabilities compared to the ITZO TFT under both positive-bias and negative-bias-illumination stresses. From the X-ray photoelectron spectroscopy O1s spectra with fitted curves for ITZO and ITZO:Mg films, we observe that Mg doping contributes to an enhancement of the oxygen bond without oxygen vacancy and a reduction of the oxygen bonds with oxygen vacancies. This result shows that the Mg can be an effective suppressor in a-ITZO TFTs.
Analysis on Self-Heating Effect in 7 nm Node Bulk FinFET Device
Yoo, Sung-Won ; Kim, Hyunsuk ; Kang, Myounggon ; Shin, Hyungcheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 204~209
DOI : 10.5573/JSTS.2016.16.2.204
The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.
A Study on Contact Resistance Reduction in Ni Germanide/Ge using Sb Interlayer
Kim, Jeyoung ; Li, Meng ; Lee, Ga-Won ; Oh, Jungwoo ; Lee, Hi-Deok ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 210~214
DOI : 10.5573/JSTS.2016.16.2.210
In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.
Diode Embedded AlGaN/GaN Heterojuction Field-Effect Transistor
Park, Sung-Hoon ; Lee, Jae-Gil ; Cho, Chun-Hyung ; Choi, Yearn-Ik ; Kim, Hyungtak ; Cha, Ho-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 215~220
DOI : 10.5573/JSTS.2016.16.2.215
Monolithically integrated devices are strongly desired in next generation power ICs to reduce the chip size and improve the efficiency and frequency response. Three examples of the embedment of different functional diode(s) into AlGaN/GaN heterojunction field-effect transistors are presented, which can minimize the parasitic effects caused by interconnection between devices.
Normally-Off Operation of AlGaN/GaN Heterojunction Field-Effect Transistor with Clamping Diode
Han, Sang-Woo ; Park, Sung-Hoon ; Kim, Hyun-Seop ; Lim, Jongtae ; Cho, Chun-Hyung ; Cha, Ho-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 221~225
DOI : 10.5573/JSTS.2016.16.2.221
This paper reports a new method to enable the normally-off operation of AlGaN/GaN heterojunction field-effect transistors (HFETs). A capacitor was connected to the gate input node of a normally-on AlGaN/GaN HFET with a Schottky gate where the Schottky gate acted as a clamping diode. The combination of the capacitor and Schottky gate functioned as a clamp circuit to downshift the input signal to enable the normally-off operation. The normally-off operation with a virtual threshold voltage of 5.3 V was successfully demonstrated with excellent dynamic switching characteristics.
Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells
Jung, Jihun ; Ansari, Muhammad Adil ; Kim, Dooyoung ; Park, Sungju ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 226~235
DOI : 10.5573/JSTS.2016.16.2.226
The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.
Critical Review of Current Trends in ASIC Writing and Layout Analysis
Vikram, Abhishek ; Agarwal, Vineeta ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 236~250
DOI : 10.5573/JSTS.2016.16.2.236
Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.
An Energy-Efficient Matching Accelerator Using Matching Prediction for Mobile Object Recognition
Choi, Seongrim ; Lee, Hwanyong ; Nam, Byeong-Gyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 2, 2016, Pages 251~254
DOI : 10.5573/JSTS.2016.16.2.251
An energy-efficient object matching accelerator is proposed for mobile object recognition based on matching prediction scheme. Conventionally, vocabulary tree has been used to save the external memory bandwidth in object matching process but involved massive internal memory transactions to examine each object in a database. In this paper, a novel object matching accelerator is proposed based on matching predictions to reduce unnecessary internal memory transactions by mitigating non-target object examinations, thereby improving the energy-efficiency. Experimental results show a 26% reduction in power-delay product compared to the prior art.