Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 16, Issue 4 - Aug 2016
Volume 16, Issue 3 - Jun 2016
Volume 16, Issue 2 - Apr 2016
Volume 16, Issue 1 - Feb 2016
Selecting the target year
Full-Wave Rectifier with Vibration Detector for Vibrational Energy Harvesting Systems
Yoon, Eun-Jung ; Yang, Min-Jae ; Park, Jong-Tae ; Yu, Chong-Gun ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 255~260
DOI : 10.5573/JSTS.2016.16.3.255
In this paper, a full-wave rectifier (FWR) with a simple vibration detector suitable for use with vibrational energy harvesting systems is presented. Conventional active FWRs where active diodes are used to reduce the diode voltage drop and increase the system efficiency are usually powered from the output. Output-powered FWRs exhibit relatively high efficiencies because the comparators used in active diodes are powered from the stable output voltage. Nevertheless, a major drawback is that these FWRs consume power from the output storage capacitor even when the system is not harvesting any energy. To overcome the problem, a technique using a simple vibration detector consisting of a peak detector and a level converter is proposed. The vibration detector detects whether vibrational energy exists or not in the input terminal and disables the comparators when there is no vibrational energy. The proposed FWR with the vibration detector is designed using a
CMOS process. Simulation results have verified the effectiveness of the proposed scheme. By using the proposed vibration detector, a decrease in leakage current by approximately 67,000 times can be achieved after the vibration disappears.
Reconfigurable FIR Filter for Dynamic Variation of Filter Order and Filter Coefficients
Meher, Pramod Kumar ; Park, Sang Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 261~273
DOI : 10.5573/JSTS.2016.16.3.261
Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.
A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS
Cho, Sunghun ; Lee, DongSoo ; Lee, Juri ; Park, Hyung-Gu ; Pu, YoungGun ; Yoo, Sang-Sun ; Hwang, Keum Cheol ; Yang, Youngoo ; Park, Cheon-Seok ; Lee, Kang-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 274~286
DOI : 10.5573/JSTS.2016.16.3.274
This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using
CMOS technology and the die area is
. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.
A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
Kwon, Dae-Hyun ; Rhim, Jinsoo ; Choi, Woo-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 287~292
DOI : 10.5573/JSTS.2016.16.3.287
A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from
PRBS input data has 0.011-UI rms jitter.
Area-Optimized Multi-Standard AES-CCM Security Engine for IEEE 802.15.4 / 802.15.6
Choi, Injun ; Kim, Ji-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 293~299
DOI : 10.5573/JSTS.2016.16.3.293
Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.
ADC-Based Backplane Receivers: Motivations, Issues and Future
Chung, Hayun ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 300~311
DOI : 10.5573/JSTS.2016.16.3.300
The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.
2-6 GHz GaN HEMT Power Amplifier MMIC with Bridged-T All-Pass Filters and Output-Reactance-Compensation Shorted Stubs
Lee, Sang-Kyung ; Bae, Kyung-Tae ; Kim, Dong-Wook ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 312~318
DOI : 10.5573/JSTS.2016.16.3.312
This paper presents a 2-6 GHz GaN HEMT power amplifier monolithic microwave integrated circuit (MMIC) with bridged-T all-pass filters and output-reactance-compensation shorted stubs using the
GaN HEMT foundry process that is developed by WIN Semiconductors, Inc. The bridged-T filter is modified to mitigate the bandwidth degradation of impedance matching due to the inherent channel resistance of the transistor, and the shorted stub with a bypass capacitor minimizes the output reactance of the transistor to ease wideband load impedance matching for maximum output power. The fabricated power amplifier MMIC shows a flat linear gain of 20 dB or more, an average output power of 40.1 dBm and a power-added efficiency of 19-26 % in 2 to 6 GHz, which is very useful in applications such as communication jammers and electronic warfare systems.
Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators
Na, Seung-in ; Kim, Susie ; Yang, Youngtae ; Kim, Suhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 319~329
DOI : 10.5573/JSTS.2016.16.3.319
High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.
Improving Energy Efficiency and Lifetime of Phase Change Memory using Delta Value Indicator
Choi, Ju Hee ; Kwak, Jong Wook ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 330~338
DOI : 10.5573/JSTS.2016.16.3.330
Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.
2.6 GHz GaN-HEMT Power Amplifier MMIC for LTE Small-Cell Applications
Lim, Wonseob ; Lee, Hwiseob ; Kang, Hyunuk ; Lee, Wooseok ; Lee, Kang-Yoon ; Hwang, Keum Cheol ; Yang, Youngoo ; Park, Cheon-Seok ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 339~345
DOI : 10.5573/JSTS.2016.16.3.339
This paper presents a two-stage power amplifier MMIC using a
GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of
and was mounted on a
QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.
Atomic Layer Deposition of TiO
using Titanium Isopropoxide and H
O: Operational Principle of Equipment and Parameter Setting
Cho, Karam ; Park, Jung-Dong ; Shin, Changhwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 346~351
DOI : 10.5573/JSTS.2016.16.3.346
Titanium dioxide (
) films are deposited by atomic layer deposition (ALD) using titanium isopropoxide (TTIP) and
as precursors. The operating instructions for the ALD equipment are described in detail, along with the settings for relevant parameters. The thickness of the
film is measured, and thereby, the deposition rate is quantitatively estimated to verify the linearity of the deposition rate.
All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
Seong, Kihwan ; Lee, Won-Cheol ; Kim, Byungsub ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 352~358
DOI : 10.5573/JSTS.2016.16.3.352
A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies
, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.
Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC
Vijayaraj, M. ; Balamurugan, K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 359~366
DOI : 10.5573/JSTS.2016.16.3.359
Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.
Electro-Thermal Modeling and Experimental Validation of Integrated Microbolometer with ROIC
Kim, Gyungtae ; Kim, Taehyun ; Kim, Hee Yeoun ; Park, Yunjong ; Ko, Hyoungho ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 367~374
DOI : 10.5573/JSTS.2016.16.3.367
This paper presents an electro-thermal modeling of an amorphous silicon (a-Si) uncooled microbolometer. This modeling provides a comprehensive solution for simulating the electro-thermal characteristics of the fabricated microbolometer and enables electro-thermal co-simulation between MEMS and CMOS integrated circuits. To validate this model, three types of uncooled microbolometers were fabricated using a post-CMOS surface micromachining process. The simulation results show a maximum discrepancy of 2.6% relative to the experimental results.
An Excessive Current Subtraction Technique to Improve Dynamic Range for Touch Screen Panel Applications
Heo, Sanghyun ; Ma, Hyunggun ; Bien, Franklin ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 375~379
DOI : 10.5573/JSTS.2016.16.3.375
A current subtraction technique with parallel operation system is proposed to remove excessive current in touch screen application. The proposed current subtraction remove the current which go into the input node of charge amplifier. The value of subtraction current is same with current when touch screen is not touched. As a result, charge amplifier output is only proportional to variation of mutual capacitor, which make dynamic rage is increased. Also, Transmitter (Tx) driving signal and subtraction driving signal are out of phase each other. Thus, noise generated in Tx is cancelled. The proposed IC is implemented in a mixed-mode 0.18-um CMOS process. Overall system is designed for touch screen panel (TSP) with 16 driving lines and 8 sensing lines. 5-V supply voltages are used in the proposed circuits. For multiple Tx driving signal, Walsh codes are used and signal frequency is 300 khz. By using proposed technique, dynamic rage is improved 36 dB.
A Compact Low-Power Shunt Proximity Touch Sensor and Readout for Haptic Function
Lee, Yong-Min ; Lee, Kye-Shin ; Jeong, Taikyeong ;
JSTS:Journal of Semiconductor Technology and Science, volume 16, issue 3, 2016, Pages 380~386
DOI : 10.5573/JSTS.2016.16.3.380
This paper presents a compact and low-power on-chip touch sensor and readout circuit using shunt proximity touch sensor and its design scheme. In the proposed touch sensor readout circuit, the touch panel condition depending on the proximity of the finger is directly converted into the corresponding voltage level without additional signal conditioning procedures. Furthermore, the additional circuitry including the comparator and the flip-flop does not consume any static current, which leads to a low-power design scheme. A new prototype touch sensor readout integrated circuit was fabricated using complementally metal oxide silicon (CMOS)
technology with core area of
and total current of
. Our measurement result shows that an actual 10.4 inches capacitive type touch screen panel (TSP) can detect the finger size from 0 to 1.52 mm, sharply.