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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 2, Issue 4 - Dec 2002
Volume 2, Issue 3 - Sep 2002
Volume 2, Issue 2 - Jun 2002
Volume 2, Issue 1 - Mar 2002
Selecting the target year
A New EEPROM with Side Floating Gates Having Different Work Function from Control Gate
Youngjoon Ahn ; Sangyeon Han ; Kim, Hoon ; Lee, Jongho ; Hyungcheol Shin ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 157~163
A new flash EEPROM device with
poly-Si control gate and
poly-Si floating side gate was fabricated and characterized. The
poly-Si gate is formed on both sides of the
poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.
Aspects of Hard Breakdown Characteristics in a 2.2-nm-thick
Komiya, Kenji ; Omura, Yasuhisa ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 164~169
This paper mainly discusses the hard breakdown of 2.2-nm-thick
films. It is shown that the hard breakdown event of a 2.2-nm-thick
film greatly depends on the applied electric field. It is strongly suggested that the local weak spots created by applying a low initial stress to a 2.2-nm-thick
film resist the onset of hard breakdown. In other words, it is anticipated that the stored electrostatic energy is fast dissipated by trap-assisted tunneling in 2.2-nm-thick
film. Consequently, it is strongly suggested that 2.2-nm-thick
films are intrinsically quite robust.
Field Effect Transistor of Vertically Stacked, Self-assembled InAs Quantum Dots with Nonvolatile Memory
Li, Shuwei ; Koike, Kazuto ; Yano, Mitsuaki ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 170~172
The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.
A Novel Sensing Circuit for 2T-2MTJ MRAM Applicable to High Speed Synchronous Operation
Jang, Eun-Jung ; Lee, Jung-Hwa ; Kim, Ji-hyun ; Lee, Seungjun ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 173~179
We propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a
logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10 ns.
Metal Gate Electrodes for Advanced CMOS Devices
Lee, S. J. ; D. L. Kwong ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 180~184
In this paper, the electrical properties of PVD Ta and
gate electrodes on
and their thermal stabilities are investigated. The results show that the work functions of
gate electrode are modified by the amount of N, which is controlled by the flow rate of
during reactive sputtering process. The thermal stability of Ta and
gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage (
), and leakage current after post-metallization anneal at high temperature in
ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for
gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.
MRAM Technology for High Density Memory Application
Kim, Chang-Shuk ; Jang, In-Woo ; Lee, Kye-Nam ; Lee, Seaung-Suk ; Park, Sung-Hyung ; Park, Gun-Sook ; Ban, Geun-Do ; Park, Young-Jin ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 185~196
MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.
Technology of MRAM (Magneto-resistive Random Access Memory) Using MTJ(Magnetic Tunnel Junction) Cell
Park, Wanjun ; Song, I-Hun ; Park, Sangjin ; Kim, Teawan ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 197~204
DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.
Metal-Organic Chemical Vapor Deposition of
Thin Films for High-Density Ferroelectric Random Access Memory Application
Lee, June-Key ; Ku, June-Mo ; Cho, Chung-Rae ; Lee, Yong-Kyun ; Sangmin Shin ; Park, Youngsoo ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 205~212
The growth characteristics of metal-organic chemical vapor deposition (MOCVD)
(PZT) thin films were investigated for the application of high-density ferroelectric random access memories (FRAM) devices beyond 64Mbit density. The supply control of Pb precursor plays the most critical role in order to achieve a reliable process for PZT thin film deposition. We have monitored the changes in the microstructure and electrical properties of films on increasing the Pb precursor supply into the reaction chamber. Under optimized conditions,
capacitor shows well-saturated hysteresis loops with a remanent polarization (Pr) of
and coercive voltage of 0.8V at 2.5V. Other issues such as step coverage, compositional uniformity and low temperature deposition was discussed in viewpoint of actual device application.
Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device
Yu, Byoung-Gon ; You, In-Kyu ; Lee, Won-Jae ; Ryu, Sang-Ouk ; Kim, Kwi-Dong ; Yoon, Sung-Min ; Cho, Seong-Mok ; Lee, Nam-Yeal ; Shin, Woong-Chul ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 213~225
Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.
Virtual ground monitoring for high fault coverage of linear analog circuits
Roh, Jeongjin ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 226~232
This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.
Optimum Design of the Interdigitated CB Structure
qiang, Yang-Hong ; bi, Chen-Xing ;
JSTS:Journal of Semiconductor Technology and Science, volume 2, issue 3, 2002, Pages 233~236
Some measures are provided for the optimum design of specific on-resistance
of interdigitated CB (Composite Buffer) MOSFET, including introducing opposite type impurity into the P region near the
contact, separating P region from N region with an oxide film, and a groove in the N region near the
contact. The new relationship between the
, which proved by numerical device simulation, are more exact and minute than the qualitative results before.