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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 3, Issue 4 - Dec 2003
Volume 3, Issue 3 - Sep 2003
Volume 3, Issue 2 - Jun 2003
Volume 3, Issue 1 - Mar 2003
Selecting the target year
Improved Breakdown Voltage Characteristics of
p-HEMT with an Oxidized GaAs Gate
I-H. Kang ; Lee, J-W. ; S-J. Kang ; S-J. Jo ; S-K. In ; H-J. Song ; Kim, J-H. ; J-I. Song ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 63~68
The DC and RF characteristics of
p-HEMTs with a gate oxide layer of various thicknesses (
) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of
was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of
suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.
Data Retention Time and Electrical Characteristics of Cell Transistor According to STI Materials in 90 nm DRAM
Shin, S.H. ; Lee, S.H. ; Kim, Y.S. ; Heo, J.H. ; Bae, D.I. ; Hong, S.H. ; Park, S.H. ; Lee, J.W. ; Lee, J.G. ; Oh, J.H. ; Kim, M.S. ; Cho, C.H. ; Chung, T.Y. ; Kim, Ki-Nam ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 69~75
Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.
Novel Robust Structure and High k Dielectric Material for 90 nm DRAM Capacitor
Park, Y.K. ; Y.S. Ahn ; Lee, K.H. ; C.H. Cho ; T.Y. Chung ; Kim, Kinam ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 76~82
The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel
dielectric material with equivalent oxide thickness (EOT) of 25
is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by
dielectric material, respectively.
CCD Image Sensor with Variable Reset Operation
Park, Sang-Sik ; Uh, Hyung-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 83~88
The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with
pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.
High Conversion Gain Q-band Active Sub-harmonic Mixer Using GaAs PHEMT
Uhm, Won-Young ; Lee, Bok-Hyung ; Kim, Sung-Chan ; Lee, Mun-Kyo ; Sul, Woo-Suk ; Yi, Sang-Yong ; Kim, Yong-Hoh ; Rhee, Jin-Koo ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 89~95
In this paper, we have designed and fabricated high conversion gain Q-band active sub-harmonic mixers for a receiver of millimeter wave wireless communication systems. The fabricated active sub-harmonic mixer uses 2nd harmonic signals of a low local oscillator (LO) frequency. The fabricated mixer was successfully integrated by using
GaAs pseudomorphic high electron mobility transistors (PHEMTs) and coplanar waveguide (CPW) structures. From the measurement, it shows that maximum conversion gain of 4.8 dB has obtained at a RF frequency of 40 GHz for 10 dBm LO power of 17.5 GHz. Conversion gain from the fabricated sub-harmonic mixer is one of the best reported thus far. And a phase noise of the 2nd harmonic was obtained -90.23 dBc/Hz at 100 kHz offset. The active sub-harmonic mixer also ensure a high degree of isolations, which are -35.8 dB from LO-to-IF and -40.5 dB from LO-to-RF, respectively, at a LO frequency of 17.5 GHz.
Investigation of Oxygen Incorporation in AlGaN/GaN Heterostructures
Jang, Ho-Won ; Baik, Jeong-Min ; Lee, Jong-Lam ; Shin, Hyun-Joon ; Lee, Jung-Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 96~101
Direct evidence on the incorporation of high concentration of oxygen into undoped AlGaN layers for the AlGaN/GaN heterostuctures is provided by scanning photoemission microscopy using synchrotron radiation. In-situ annealing at
resulted in a significant increase in the oxygen concentration at the AlGaN surface due to the predominant formation of Al-O bonds. The oxygen incorporation into the AlGaN layers resulting from the high reactivity of Al to oxygen can enhance the tunneling-assisted transport of electrons at the metal/AlGaN interface, leading to the reduction of the Schottky barrier height and the increase of the sheet carrier concentration near the AlGaN/GaN interface.
Dual Edge-Triggered NAND-Keeper Flip-Flop for High-Performance VLSI
Kim, Jae-Il ; Kong, Bai-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 2, 2003, Pages 102~106
This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a
CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.