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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 3, Issue 4 - Dec 2003
Volume 3, Issue 3 - Sep 2003
Volume 3, Issue 2 - Jun 2003
Volume 3, Issue 1 - Mar 2003
Selecting the target year
Process-Structure-Property Relationship and its Impact on Microelectronics Device Reliability and Failure Mechanism
Tung, Chih-Hang ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 107~113
Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.
Stress and Stress Voiding in Cu/Low-k Interconnects
Paik, Jong-Min ; Park, Hyun ; Joo, Young-Chang ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 114~121
Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.
Some Characteristics of Anisotropic Conductive and Non-conductive Adhesive Flip Chip on Flex Interconnections
Caers, J.F.J.M. ; De Vries, J.W.C. ; Zhao, X.J. ; Wong, E.H. ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 122~131
In this study, some characteristics of conductive and non-conductive adhesive inter-connections are derived, based on data from literature and own projects. Assembly of flip chip on flex is taken as a carrier. Potential failure mechanisms of adhesive interconnections reported in literature are reviewed. Some methods that can be used to evaluate the quality of adhesive interconnections and to evaluate their aging behavior are given. Possible finite element simulation approaches are introduced and the required critical materials properties are summarized. Response to temperature and moisture, resistance to reflow soldering and resistance to rapid change in temperature and humidity are elaborated. The effect of post cure during accelerated testing is discussed. This study shows that only a combined approach using finite element simulations, and use of appropriate experimental evaluation methods can result in revealing, understanding and quantifying the complex degradation mechanisms of adhesive interconnections during aging.
Comparison of retention characteristics of ferroelectric capacitors with
films deposited by various methods for high-density non-volatile memory.
Sangmin Shin ; Mirko Hofmann ; Lee, Yong-Kyun ; Koo, June-Mo ; Cho, Choong-Rae ; Lee, June-Key ; Park, Youngsoo ; Lee, Kyu-Mann ; Song, Yoon-Jong ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 132~138
We investigated the polarization retention characteristics of ferroelectric capacitors with
(PZT) thin films which were fabricated by different deposition methods. In thermally-accelerated retention tests, PZT films which were prepared by a chemical solution deposition (CSD) method showed rapid decay of retained polarization charges as the thickness of the films decreased down to 100 nm, while the films which were grown by metal organic chemical vapor deposition (MOCVD) retained relatively large non-volatile charges at the corresponding thickness. We concluded that in the CSD-grown films, the thicker interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of these layers was larger in MOCVD-grown films than in CSD-grown films. Due to incomplete compensation of surface polarization charges by the free charges in the metal electrodes, the interfacial field activated the space charges inside the interfacial layers and deposited them at the boundary between the ferroelectric layer and the interfacial layer. Such space charges built up an internal field inside the films, which interfered with domain wall motion, so that retention property at last became degraded. We observed less imprint which was a result of less internal field in MOCVD-grown films while large imprint was observed in CSD-grown films.
Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-l00nm Technology
Navakanta Bhat ; Thakur, Chandrabhan-Singh ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 139~144
We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.
Electrical Characteristics of InAlAs/InGaAs/InAlAs Pseudomorphic High Electron Mobility Transistors under Sub-Bandgap Photonic Excitation
Kim, H.T. ; Kim, D.M. ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 145~152
Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv
, and optical power(
)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage (
) and the onset voltage for the impact ionization (
) have been extracted and empirical model for their dependence on the
have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with
, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.
Electrostatic Discharge (ESD) and Failure Analysis: Models, Methodologies and Mechanisms for CMOS, Silicon On Insulator and Silicon Germanium Technologies
Voldman, Steven H. ;
JSTS:Journal of Semiconductor Technology and Science, volume 3, issue 3, 2003, Pages 153~166
Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.