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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 4, Issue 4 - Dec 2004
Volume 4, Issue 3 - Sep 2004
Volume 4, Issue 2 - Jun 2004
Volume 4, Issue 1 - Mar 2004
Selecting the target year
FinFET for Terabit Era
Choi, Yang-Kyu ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 1~11
A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.
Design Consideration of Body-Tied FinFETs (
MOSFETs) Implemented on Bulk Si Wafers
Han, Kyoung-Rok ; Choi, Byung-Gil ; Lee, Jong-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 12~17
The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of
, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.
Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs
Avci, Uygar ; Kumar, Arvind ; Tiwari, Sandip ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 18~26
Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.
Gate Tunneling Current and QuantumEffects in Deep Scaled MOSFETs
Choi, Chang-Hoon ; Dutton, Robert W. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 27~31
Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated
of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.
Simulation of Quantum Effects in the Nano-scale Semiconductor Device
Jin, Seong-Hoon ; Park, Young-June ; Min, Hong-Shick ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 32~40
An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the
interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.
CMOS Compatible Fabrication Technique for Nano-Transistors by Conventional Optical Lithography
Horst, C. ; Kallis, K.T. ; Horstmann, J.T. ; Fiedler, H.L. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 41~44
The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.
Flowable oxide CVD Process for Shallow Trench Isolation in Silicon Semiconductor
Chung, Sung-Woong ; Ahn, Sang-Tae ; Sohn, Hyun-Chul ; Lee, Sang-Don ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 45~51
We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.
Device and Circuit Performance Issues with Deeply Scaled High-K MOS Transistors
Rao, V. Ramgopal ; Mohapatra, Nihar R. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 52~62
In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin
or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.
A Simple Analytical Model for the Study of Optical Bistability Using Multiple Quantum Well p-i-n Diode Structure
Jit, S. ; Pal, B.B. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 63~73
A simple analytical model has been presented for the study of the optical bistability using a
multiple quantum well (MQW) p-i-n diode structure. The calculation of the optical absorption is based on a semi-emperical model which is accurately valid for a range of wells between 5 and 20 nm and the electric field F< 200kV/cm . The electric field dependent analytical expression for the responsivity is presented. An attempt has been made to derive the analytical relationship between the incident optical power (
) and the voltage V across the device when the diode is reverse biased by a power supply in series with a load resistor. The relationship between
(i.e. transmitted optical power) is also presented. Numerical results are presented for a typical case of well size
optical wave length l = 851.7nm and electric field F? 100kV/cm. It has been shown that for the values of
within certain range, the device changes its state in such a way that corresponding to every value of
, two stable states and one unstable state of V as well as of
are obtained which shows the optically controlled bistable nature of the device.
Microwave Photonics Frequency-Converted Link Using Electroabsorption Devices
Wu, Y. ; Shin, D.S. ; Chang, W.S.C. ; Yu, P.K.L. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 1, 2004, Pages 74~81
We propose a novel scheme to transmit high center frequency RF signals using electroabsorption devices (EADs) as frequency converters at the transmitter and the receiver. In this approach frequency heterodyning is employed for obtaining high center frequency. With the EAD as a detector/mixer at the receiver we demonstrated a smaller conversion loss than that of the conventional modulator/mixer. With EAD as a modulator/mixer at the transmitter and with two heterodyned lasers to generate an optical local oscillator (LO), we demonstrated a large reduction (
) in conversion loss, and the transmission is not limited by the optical saturation of the EAD. This transmission scheme has optical single-side-band transmission feature which greatly relieves the fiber dispersion effect.