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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 4, Issue 4 - Dec 2004
Volume 4, Issue 3 - Sep 2004
Volume 4, Issue 2 - Jun 2004
Volume 4, Issue 1 - Mar 2004
Selecting the target year
MOSFET Model HiSIM Based on Surface-Potential Description for Enabling Accurate RF-CMOS Design
Miura-Mattausch, M. ; Mattausch, H.J. ; Ohguro, T. ; Iizuka, T. ; Taguchi, M. ; Kumashiro, S. ; Miyamoto, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 133~140
The origin of the phenomena, obstructing circuit performance in the RF operating regime, as well as their modeling will be discussed. The applied surface-potential-based modeling allows self-consistent description of all phenomena important for accurate circuit simulation, as demonstrated with the MOSFET model HiSIM.
Accurate Compact MOSFET Modeling Scheme for Harmonic Distortion Analysis
Iniguez, B. ; Picos, R. ; Kwon, I. ; Shur, M.S. ; Fjeldly, T.A. ; Lee, K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 141~148
We discuss and develop a compact MOSFET modeling scheme in order to obtain accurate descriptions of the drain current and its derivatives up to the 5th order. We have analyzed the physical effects which govern the behaviour of the 3rd derivative in long and deep-subrnicron channel MOSFETs. Our modeling agrees well with experimental data and describes continuous transitions between operating regimes, thanks to the use of continuous functions, which do not introduce any artificial peaks.
On-Chip Spiral Inductors for RF Applications: An Overview
Chen, Ji ; Liou, Juin J. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 149~167
Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC's such as low-noise amplifiers and oscillators. This paper gives a broad overview on the on-chip spiral inductors. The design concept and modeling approach of the typical square-shaped spiral inductor are first addressed. This is followed by the discussions of advanced structures for the enhancement of inductor performance. Research works reported in the literature are summarized to aid the understanding of the recent development of such devices.
Optimization of Low Power CMOS Baseband Analog Filter-Amplifier Chain for Direct Conversion Receiver
Lee, Min-Kyung ; Kwon, Ick-Jin ; Lee, Kwy-Ro ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 168~173
A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in
CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.
System Level Design of Multi-standard Receiver Using Reconfigurable RF Block
Kim, Chang-Jae ; Jang, Young-Kyun ; Yoo, Hyung-Joun ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 174~181
In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at
GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation,
GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.
A System-in-Package (SiP) Integration of a 62GHz Transmitter for MM-wave Communication Terminals Applications
Lee, Young-Chul ; Park, Chul-Soon ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 182~188
We demonstrate a
sized compact transmitter using LTCC System-in-Package (SiP) technology for 60GHz-band wireless communication applications. For low-attenuation characteristics and resonance suppression of the SiP, we have proposed and demonstrated a coplanar double wire-bond transition and novel CPW-to-stripline transition integrating air-cavities as well as novel air-cavities embedded CPW line. The fabricated transmitter achieves an output of 13dBm at a RF frequency of 62GHz, an IF frequency of 2.4GHz, and a LO frequency of 59.6GHz. The up-conversion gain is 11dB, while the LO signal is suppressed with the image rejection mixer below -21.4dBc, and the image and spurious signals are also suppressed below -31dBc.
A Wafer Level Packaged Limiting Amplifier for 10Gbps Optical Transmission System
Ju, Chul-Won ; Min, Byoung-Gue ; Kim, Seong-Il ; Lee, Kyung-Ho ; Lee, Jong-Min ; Kang, Young-Il ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 189~195
A 10 Gb/s limiting amplifier IC with the emitter area of
for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the
pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to
with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.
Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals
Gutmann, R.J. ; Zeng, A.Y. ; Devarajan, S. ; Lu, J.Q. ; Rose, K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 196~203
A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.
Partial Matched Filter for Low Power and Fast Code Acquisition of DSSS-CPFSK Signals
Park, Hyung-Chul ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 204~209
A partial matched filter (PMF) for semi-coherent correlation code acquisition of the DSSS-CPFSK signal is proposed. It is a calculation-reduced structure of the hard-limited signal based FIR filter, yet its code acquisition time is equal to that of the hard-limited signal based FIR filter. The PMF eliminates duplicate calculations by utilizing the characteristic that the hard-limited DSSS-CPFSK signal has same value in several consecutive samples. For example, the PMF can achieve about 95% reduction in gate size, as compared to the hard-limited signal based FIR filter, when the modulation index of the DSSS-CPFSK signal is equal to 1.5 and the sample rate is equal to 40 sample/chip.
A Noncoherent UWB Communication System for Low Power Applications
Yang, Suck-Chel ; Park, Jung-Wan ; Moon, Yong ; Lee, Won-Cheol ; Shin, Yo-An ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 210~216
In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.
High -Rate Laser Ablation For Through-Wafer Via Holes in SiC Substrates and GaN/AlN/SiC Templates
Kim, S. ; Bang, B.S. ; Ren, F. ; d'Entremont, J. ; Blumenfeld, W. ; Cordock, T. ; Pearton, S.J. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 217~221
]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870
were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500
with a Q-switched pulse width of
nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3
) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.
Cell Signal Distribution Characteristics For High Density FeRAM
Kang, Hee-Bok ; Park, Young-Jin ; Lee, Jae-Jin ; Ahn, Jin-Hong ; Sung, Man-Young ; Sung, Young-Kwon ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 222~227
The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of
and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than
Optimization of Gate Stack MOSFETs with Quantization Effects
Mangla, Tina ; Sehgal, Amit ; Saxena, Manoj ; Haldar, Subhasis ; Gupta, Mridula ; Gupta, R.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 228~239
In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of
dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and
characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.
Optimization of InAlAs/InGaAs HEMT Performance for Microwave Frequency Applications and Reliability
Gupta, Ritesh ; Aggarwal, Sandeep Kumar ; Gupta, Mridula ; Gupta, R.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 3, 2004, Pages 240~249
In the present paper efforts have been made to optimize InAlAs/InGaAs HEMT by enhancing the effective gate voltage (
) using pulsed doped structure from uniformly doped to delta doped for microwave frequency applications and reliability. The detailed design criteria to select the proper design parameters have also been discussed in detail to exclude parallel conduction without affecting the del ice performance. Then the optimized value of
and breakdown voltages corresponding to maximum value of transconductance has been obtained. These values are then used to predict the transconductance and cut-off frequency of the del ice for different channel depths and gate lengths.