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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 4, Issue 4 - Dec 2004
Volume 4, Issue 3 - Sep 2004
Volume 4, Issue 2 - Jun 2004
Volume 4, Issue 1 - Mar 2004
Selecting the target year
Development of Embedded Non-Volatile FRAMs for High Performance Smart Cards
Lee, Kang-Woon ; Jeon, Byung-Gil ; Min, Byung-Jun ; Oh, Seung-Gyu ; Lee, Han-Ju ; Lim, Woo-Taek ; Cho, Sung-Hee ; Jeong, Hong-Sik ; Chung, Chil-Hee ; Kim, Ki-Nam ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 251~257
Nonvolatile FRAMs with a design rule of 0.18
were developed for the high performance smart card. A 1Mb FRAM was embedded in place of an EEPROM and a 64Kb FRAM was embedded in place of a. SRAM. It was confirmed that the FRAMs performed the roles of the EEPROM and SRAM successfully using the asynchronous write/read operation method and the one time programming (OTP) scheme. The cycle time of the FRAM was 10 MHz, which remarkably improved the write performance of the smart card in comparison with that of the conventional smart card with an EEPROM. Additionally, a simple and smart bit-line reference scheme for the future FRAM device having a 1T1C cell type was proposed.
A Network Storage LSI Suitable for Home Network
Lim, Han-Kyu ; Han, Ji-Ho ; Jeong, Deog-Kyoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 258~262
Storage over Ethernet (SoE) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike SAN, no server computer intervenes between the storage and the client hosts. We propose a SoE disk controller (SoEDC) amenable to low-cost, single-chip implementation that processes a simplified L3/L4 protocol and converts commands between Ethernet and ATA/ATAPI, while the rest of the complex tasks are performed by the remote hosts. Thanks to simple architecture and protocol, the SoEDC implemented on a single
chip in 0.18um CMOS technology achieves maximum throughput of 55MB/s on Gigabit Ethernet, which is comparable to that of a high-performance disk storage locally attached to a host computer.
MTCMOS Post-Mask Performance Enhancement
Kim, Kyo-Sun ; Won, Hyo-Sig ; Jeong, Kwang-Ok ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 263~268
In this paper, we motivate the post-mask performance enhancement technique combined with the Multi-Threshold Voltage CMOS (MTCMOS) leakage current suppression technology, and integrate the new design issues related to the MTCMOS technology into the ASIC design methodology. The issues include short-circuit current and sneak leakage current prevention. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um process. The fabricated PDA processor operates at 333MHz which has been improved about 23% at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.
Accuracy of Current Delivery System in Current Source Data-Driver IC for AM-OLED
Hattori, Reiji ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 269~274
Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3
with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.
1 Gb/s gated-oscillator burst mode CDR for half-rate clock recovery
Han, Pyung-Su ; Choi, Woo-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 275~279
A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.
A 9-bit ADC with a Wide-Range Sample-and-Hold Amplifier
Lim, Jin-Up ; Cho, Young-Joo ; Choi, Joong-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 280~285
In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-
CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.
Exploring On-Chip Bus Architectures for Multitask Applications
Kim, Sung-Chan ; Ha, Soon-Hoi ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 286~292
In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks are mapped. To apply it to multitask applications, the concurrent execution of the function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effects of other tasks with respect to bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for on-chip bus architectures, Its viability and efficiency are validated by a preliminary example.
Design and Analysis of Linear Channel-Selection Filter for Direct Conversion Receiver
Jin, Sang-Su ; Ryu, Seong-Han ; Kim, Hui-Jung ; Kim, Bum-Man ; Lee, Jong-Ryul ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 293~299
An active RC 2nd order Butterworth filter suitable for a baseband channel-selection filter of a direct conversion receiver is presented. The linearity of the 2nd order Butterworth filter is analyzed. In order to improve the linearity of the filter, the operational amplifiers should have a high linear gain and low 3rd harmonic, and the filter should be designed to have large feedback factor. This second order Butterworth filter achieves-14dBV in-channel (400kHz, 500kHz) IIP3, +29dBV out-channel (10MHz, 20.2MHz) IIP3 and 15.6
input-referred noise and dissipates 10.8mW from a 2.7-V supply. The analysis and experimental results are in good agreement
A Micromachined Two-state Bandpass Filter using Series Inductors and MEMS Switches for WLAN Applications
Kim, Jong-Man ; Lee, Sang-Hyo ; Park, Jae-Hyoung ; Kim, Jung-Mu ; Baek, Chang-Wook ; Kwon, Young-Woo ; Kim, Yong-Kweon ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 300~306
This paper reports a novel tunable bandpass filter using two-state switched inductor with direct-contact MEMS switches for wireless LAN applications. In our filter configuration, the switched inductor is implemented to obtain more stable and much larger frequency tuning ratio compared with variable capacitor-based tunable filter. The proposed tunable filter was fabricated using a micromachining technology and electrical performances of the fabricated filter were measured. The filter consists of spiral inductors, MIM capacitors and direct-contact type MEMS switches, and its frequency tunability is achieved by changing the inductance that is induced by ON/OFF actuations of the MEMS switches. The actuation voltage of the MEMS switches was measured of 58 V, and they showed the insertion loss of 0.1 dB and isolation of 26.3 dB at 2 GHz, respectively. The measured center frequencies of the fabricated filter were 2.55 GHz and 5.1 GHz, respectively. The passband insertion loss and 3-dB bandwidth were 4.2 dB and 22.5 % at 2.55 GHz, and 5.2 dB and 23.5 % at 5.1 GHz, respectively.
Efficient Hardware Architecture of SEED S-box for Smart Cards
Hwang, Joon-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 307~311
This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in
to composite field
where more efficient computations can be implemented and transform the computed result back to
. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.
Magnetism in Fe-implanted ZnO
Heo, Y.W. ; Kelly, J. ; Norton, D.P. ; Hebard, A.F. ; Pearton, S.J. ; Zavada, J.M. ; Park, Y.D. ;
JSTS:Journal of Semiconductor Technology and Science, volume 4, issue 4, 2004, Pages 312~317
High dose (
) implantation of Fe or Ni ions into bulk, single-crystal ZnO substrates was carried out at substrate temperature of
to avoid amorphization of the implanted region. The samples were subsequently annealed at
to repair some of the residual implant damage. X-Ray Diffraction did not show any evidence of secondary phase formation in the ZnO. The Ni implanted samples remained paramagnetic but the Fe-implanted ZnO showed evidence of ferromagnetism with an approximate Curie temperature of
240K. Preliminary X-Ray Photoelectron Spectroscopy measurements showed the Fe to be ill the 2+ oxidation state. The earrler density in the implanted region still appears to be too low to support carrier-meditated origin of the ferromagnetism and formation of bound magnetic polarons may be one potential explanation for the observed magnetic properties, No evidence of the Anomalous Hall Effect could be found in the Fe-implanted ZnO, but its transport properties were dominated by the conventional or ordinary Hall effect.