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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 5, Issue 4 - Dec 2005
Volume 5, Issue 3 - Sep 2005
Volume 5, Issue 2 - Jun 2005
Volume 5, Issue 1 - Mar 2005
Selecting the target year
Characteristics of Schottky Diode and Schottky Barrier Metal-Oxide-Semiconductor Field-Effect Transistors
Jang, Moon-Gyu ; Kim, Yark-Yeon ; Jun, Myung-Sim ; Lee, Seong-Jae ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 69~76
Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as
, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by
annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.
Enhanced Hole Injections in Organic Light Emitting Diode using Rhodium Oxide Coated Anode
Kim, Soo-Young ; Choi, Ho-Won ; Kim, Kwang-Young ; Tak, Yoon-Heung ; Lee, Jong-Lam ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 77~82
We compare electrical and optical properties of organic light emitting diodes (OLEDs) using rhodium-oxide-coated indium-tin-oxide (
-Rh/ITO) to that using
-plasma-treated ITO (ITO) anodes. The turn-on voltage decreased from 7 V to 5 V and luminance value increased when the
plasma treated Rh layer was deposited on ITO. Synchrotron radiation photoelectron spectroscopy results showed the dipole energies of both ITO and
-Rh/ITO were same with each other, - 0.3 eV, meaning the formation of same amount of interface dipole. The secondary electron emission spectra revealed that the work function of
-Rh/ITO is higher hy 0.2 eV than that of ITO, resulting in the decrease of the tum-on voltage via reduction ofhole injection barrier.
Characterizations of Interface-state Density between Top Silicon and Buried Oxide on Nano-SOI Substrate by using Pseudo-MOSFETs
Cho, Won-Ju ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 83~88
The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over
, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.
ViP: A Practical Approach to Platform-based System Modeling Methodology
Um, Jun-Hyung ; Hong, Sung-Pack ; Kim, Young-Taek ; Chung, Eui-Young ; Choi, Kyu-Myung ; Kong, Jeong-Taek ; Eo, Soo-Kwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 89~101
Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.
A Low Dark Current CMOS Image Sensor Pixel with a Photodiode Structure Enclosed by P-well
Han, Sang-Wook ; Kim, Seong-Jin ; Yoon, Eui-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 102~106
A low dark current CMOS image sensor (CIS) pixel without any process modification is developed. Dark current is mainly generated at the interface region of shallow trench isolation (STI) structure. Proposed pixel reduces the dark current effectively by separating the STI region from the photodiode junction using simple layout modification. Test sensor array that has both proposed and conventional pixels is fabricated using 0.18 m CMOS process and the characteristics of the sensor are measured. The result shows that the dark current of the proposed pixel is 0.93fA/pixel that is two times lower than the conventional design.
Device Characteristics of AlGaN/GaN MIS-HFET using
Based High-k Dielectric
Park, Ki-Yeol ; Cho, Hyun-Ick ; Lee, Eun-Jin ; Hahm, Sung-Ho ; Lee, Jung-Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 107~112
We present an AlGaN/GaN metal-insulator-semiconductor-heterostructure field effect transistor (MIS-HFET) with an
laminated high-k dielectric, deposited by plasma enhanced atomic layer deposition (PEALD). Based on capacitance-voltage measurements, the dielectric constant of the deposited
laminated layer was estimated to be as high as 15. The fabricated MIS-HFET with a gate length of 102 m exhibited a maximum drain current of 500 mA/mm and maximum tr-ansconductance of 125 mS/mm. The gate leakage current was at least 4 orders of magnitude lower than that of the reference HFET. The pulsed current-voltage curve revealed that the
laminated dielectric effectively passivated the surface of the device.
4H-SiC Planar MESFET for Microwave Power Device Applications
Na, Hoon-Joo ; Jung, Sang-Yong ; Moon, Jeong-Hyun ; Yim, Jeong-Hyuk ; Song, Ho-Keun ; Lee, Jae-Bin ; Kim, Hyeong-Joon ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 113~119
4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.
Theoretical Calculation and Experimental Verification of the Hf/Al Concentration Ratio in Nano-mixed
Films Prepared by Atomic Layer Deposition
Kil, Deok-Sin ; Yeom, Seung-Jin ; Hong, Kwon ; Roh, Jae-Sung ; Sohn, Hyun-Cheol ; Kim, Jin-Woong ; Park, Sung-Wook ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 120~126
We have proposed a characteristic method to estimate real composition when multi component oxide films are deposited by ALD. Final atomic concentration ratio was theoretically calculated from the film densities and growth rates for
using ALD processed HfxAhOz mms.W e have transformed initial source feeding ratio during deposition to fins] atomic ratio in
films through thickness factors (
) ami concentration factor(C) defined in our experiments. Initial source feeding ratio could be transformed into the thickness ratio by each thickness factor. Final atomic ratio was calculated from thickness ratio by concentration factor. It has been successfully confirmed that the predicted atomic ratio was in good agreement with the actual measured value by ICP-MS analysis.
Green and Blue Light Emitting InN/GaN Quantum Wells with Nanosize Structures Grown by Metalorganic Chemical Vapor Deposition
Kim, Je-Won ; Lee, Kyu-Han ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 127~130
The structural and electrical properties of InN/GaN multiple quantum wells, which were grown by metalorganic chemical vapor deposition, were characterized by transmission electron microscopy and electroluminescence measurements. As the quantum well growth time was changed, the wavelength was varied from 451 to 531 nm. In the varied current conditions, the blue LED with the InN MQW structures did not have the wavelength shift. With this result, we can expect that the white LEDs with the InN MQW structures do not show the color temperature changes with the variations of applied currents.
Comparison of Surface Passivation Layers on InGaN/GaN MQW LEDs
Yang, Hyuck-Soo ; Han, Sang-Youn ; Hlad, M. ; Gila, B.P. ; Baik, K.H. ; Pearton, S.J. ; Jang, Soo-Hwan ; Kang, B.S. ; Ren, F. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 131~135
The effect of different surface passivation films on blue or green (465-505 nm) InGaN/GaN multi-quantum well light-emitting diodes (LEDs) die were examined.
deposited by plasma enhanced chemical vapor deposition, or
or MgO deposited by rf plasma enhanced molecular beam epitaxy all show excellent passivation qualities. The forward current-voltage (I-V) characteristics were all independent of the passivation film used, even though the MBE-deposited films have lower interface state densities (
) compared to the PECVD films (
), The reverse I-V characteristics showed more variation, hut there was no systematic difference for any of the passivation films, The results suggest that simple PECVD processes are effective for providing robust surface protection for InGaN/GaN LEDs.
A Design Evaluation of Strained Si-SiGe on Insulator (SSOI) Based Sub-50 nm nMOSFETs
Nawaz, Muhammad ; Ostling, Mikael ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 2, 2005, Pages 136~147
A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness (
of 5 and
of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.