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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 5, Issue 4 - Dec 2005
Volume 5, Issue 3 - Sep 2005
Volume 5, Issue 2 - Jun 2005
Volume 5, Issue 1 - Mar 2005
Selecting the target year
Fabrication, Estimation and Trypsin Digestion Experiment of the Thermally Isolated Micro Teactor for Bio-chemical Reaction
Sim, Tae-Seok ; Kim, Dae-Weon ; Kim, Eun-Mi ; Joo, Hwang-Soo ; Lee, Kook-Nyung ; Kim, Byung-Gee ; Kim, Yong-Hyup ; Kim, Yong-Kweon ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 149~158
This paper describes design, fabrication, and application of the silicon based temperature controllable micro reactor. In order to achieve fast temperature variation and low energy consumption, reaction chamber of the micro reactor was thermally isolated by etching the highly conductive silicon around the reaction chamber. Compared with the model not having thermally isolated structure, the thermally isolated micro reactor showed enhanced thermal performances such as fast temperature variation and low energy consumption. The performance enhancements of the micro reactor due to etched holes were verified by thermal experiment and numerical analysis. Regarding to 42 percents reduction of the thermal mass achieved by the etched holes, approximately 4 times faster thermal variation and 5 times smaller energy consumption were acquired. The total size of the fabricated micro reactor was
. Microchannel and reaction chamber were formed on the silicon substrate. The openings of channel and chamber were covered by the glass substrate. The Pt electrodes for heater and sensor are fabricated on the backside of silicon substrate below the reaction chamber. The dimension of channel cross section was
. The volume of reaction chamber was
. The temperature of the micro reactor was controlled and measured simultaneously with NI DAQ PCI-MIO-16E-l board and LabVIEW program. Finally, the fabricated micro reactor and the temperature control system were applied to the thermal denaturation and the trypsin digestion of protein. BSA(bovine serum albumin) was chosen for the test sample. It was successfully shown that BSA was successfully denatured at
for 1 min and digested by trypsin at
for 10 min.
Physics-based Algorithm Implementation for Characterization of Gate-dielectric Engineered MOSFETs including Quantization Effects
Mangla, Tina ; Sehgal, Amit ; Saxena, Manoj ; Haldar, Subhasis ; Gupta, Mridula ; Gupta, R.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 159~167
Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the
and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.
A Novel Adaptive Biasing Scheme for CMOS Op-Amps
Kurkure Girish ; Dutta Aloke K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 168~172
In this paper, we present a new adaptive biasing scheme for CMOS op-amps. The designed circuit has been used in an Operational Transconductance Amplifier (OTA) with
V power supply, and it has improved the positive and negative slew rates from 2.92 V/msec to 1242 V/msec and from 1.56 V/msec to 133 V/msec respectively, while maintaining all the small-signal performance parameter values the same as that without adaptive biasing (as expected), however, there was a marginal decrease of the dynamic range. The most useful features of the proposed circuit are that it uses a very low number of components (thus not creating severe area penalty) and requires only 25 nW of extra stand-by power.
A 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Ion-Implanted Silicon MESFET's
Jit, S. ; Morarka, Saurabh ; Mishra, Saurabh ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 173~181
A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.
Properties of Inclined Silicon Carbide Thin Films Deposited by Vacuum Thermal Evaporation
Hamadi Oday A. ; Yahia Khaled Z. ; Jassim Oday N.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 182~186
In this work, thermal evaporation system was employed to deposit thin films of SiC on glass substrates in order to determine the parameters of them. Measurements included transmission, absorption, Seebak effect, resistivity and conductivity, absorption coefficient, type of energy band-gap, extinction coefficient as functions of photon energy and the effect of increasing film thickness on transmittance. Results explained that SiC thin film is an n-type semiconductor of indirect energy band-gap of
, cut-off wavelength of 448nm, absorption coefficient of
and extinction coefficient of 0.154. The experimental measured values are in good agreement with the typical values of SiC thin films prepared by other advanced deposition techniques.
Analysis of 1/f Noise in Fully Depleted n-channel Double Gate SOI MOSFET
Kushwaha Alok ; Pandey Manoj Kumar ; Pandey Sujata ; Gupta A.K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 187~194
An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent
is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to
technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.
Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell
Cho, Seong-Jae ; Park, Il-Han ; Kim, Tae-Hun ; Lee, Jung-Hoon ; Lee, Jong-Duk ; Shin, Hyung-Cheol ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 195~203
Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.
A Small Size Broadband MEMS Antenna for 5 GHz WLAN Applications
Kim, Ji-Hyuk ; Kim, Hyeon-Cheol ; Chun, Kuk-Jin ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 204~209
A small size broadband microstrip patch antenna with small ground plane has been fabricated using MEMS. Multiple layer substrates are used to realize small size and broadband characteristics. The microstrip patch is divided into 3 pieces and each patch is connected to each other using a metal microstrip line. The fabrication process is simple and only one mask is needed. Two types of microtrip antennas are fabricated. Type A is the micros trip antenna with metal lines and type B is the microstrip antenna without metal lines. The size of proposed microstip antenna is
and the experimental results show that the antenna type A and type B have the bandwidth of 420 MHz at 5.3 GHz and 480 MHz at 5.66 GHz, respectively.
V-band Self-heterodyne Wireless Transceiver using MMIC Modules
An, Dan ; Lee, Mun-Kyo ; Lee, Sang-Jin ; Ko, Du-Hyun ; Jin, Jin-Man ; Kim, Sung-Chan ; Kim, Sam-Dong ; Park, Hyun-Chang ; Park, Hyung-Moo ; Rhee, Jin-Koo ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 3, 2005, Pages 210~219
We report on a low-cost V-band wireless transceiver with no use of any local oscillator in the receiver block using a self-heterodyne architecture. V-band millimeter-wave monolithic IC (MMIC) modules were developed to demonstrate the wireless transceiver using coplanar waveguide (CPW) and GaAs PHEMT technologies. The MMIC modules such as the MMIC low noise amplifier (LNA), medium power amplifier (MPA) and the up/down-mixer were installed in the transceiver system. To interface the MMIC chips with the component modules for the transceiver system, CPW-to-waveguide fin-line transition modules of WR-15 type were designed and fabricated. The fabricated LNA modules showed a
gain of 8.4 dB and a noise figure of 5.6 dB at 58 GHz. The MPA modules exhibited a gain of 6.9 dB and a
of 5.4 dBm at 58 GHz. The conversion losses of the up-mixer and the down-mixer module were 14.3 dB at a LO power of 15 dBm, and 19.7 dB at a LO power of 0 dBm, respectively. From the measurement of V-band wireless transceiver, a conversion gain of 0.2 dB and a
of 5.2 dBm were obtained in the transmitter block. The receiver block showed a conversion gain of 2.1 dB and a
of -18.6 dBm. The wireless transceiver system demonstrated a successful data transfer within a distance of 5 meters.