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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 5, Issue 4 - Dec 2005
Volume 5, Issue 3 - Sep 2005
Volume 5, Issue 2 - Jun 2005
Volume 5, Issue 1 - Mar 2005
Selecting the target year
An Industrial Case Study of the ARM926EJ-S Power Modeling
Kim, Hyun-Suk ; Kim, Seok-Hoon ; Lee, Ik-Hwan ; Yoo, Sung-Joo ; Chung, Eui-Young ; Choi, Kyu-Myung ; Kong, Jeong-Taek ; Eo, Soo-Kwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 221~228
In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.
System Level Architecture Evaluation and Optimization: an Industrial Case Study with AMBA3 AXI
Lee, Jong-Eun ; Kwon, Woo-Cheol ; Kim, Tae-Hun ; Chung, Eui-Young ; Choi, Kyu-Myung ; Kong, Jeong-Taek ; Eo, Soo-Kwan ; Gwilt, David ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 229~236
This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.
ASIP Instructions and Their Hardware Architecture for H.264/AVC
Lee, Jung-H. ; Kim, Sung-D. ; Sunwoo, Myung-H. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 237~242
H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about
. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.
Embedded Real-Time Software Architecture for Unmanned Autonomous Helicopters
Hong, Won-Eui ; Lee, Jae-Shin ; Rai, Laxmisha ; Kang, Soon-Ju ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 243~248
The UAV (Unmanned Aerial Vehicle) systems like unmanned autonomous helicopters are used in various missions of flight navigation and used to collect the environmental information of the surroundings. To realize the full functionalities of the UAV, the software part becomes a challenging problem. In this paper embedded real-time software architecture for unmanned autonomous helicopter is proposed that guarantee real-time performance of hard-real time tasks and re-configurability of soft-real time and non-real time tasks. The proposed software architecture has four layers: hardware, execution, service agent and remote user interface layer according to the reactiveness level for external events. In addition, the layered separation of concurrent tasks makes different kinds of mission reconfiguration possible in the system. An Unmanned autonomous helicopter system was implemented (Kyosho RC Helicopter) in our lab to test and evaluate the performance of the proposed system.
A System-on-a-Chip Design for Digital TV
Rhee, Seung-Hyeon ; Lee, Hun-Cheol ; Kim, Sang-Hoon ; Choi, Byung-Tae ; Lee, Seok-Soo ; Choi, Seung-Jong ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 249~254
This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.
Giga-Hertz-Level Electromagnetic Field Analysis for Equivalent Inductance Modeling of High-Performance SoC and SiP Designs
Yao Jason J. ; Chang Keh-Jeng ; Chuang Wei-Che ; Wang, Jimmy S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 255~261
With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.
A Novel Memory Hierarchy for Flash Memory Based Storage Systems
Yim, Keno-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 262~269
Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.
Design and Implementation of a Linux-based Smartphone
Shin, Dong-Yun ; Lim, Sung-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 270~275
As the features of mobile phones are being enhanced and the performance is being greatly improved, the generic operating systems are being incrementally used in mobile phones. However, since the mobile phones have different requirements in both features and performance compared with desktop or server systems, the operating systems for generic systems could not be used without customization and modification. This case study paper describes the design and implementation of a Linux-based smartphone hardware and software. The enhancements and additional implementations in both kernel and middleware layers are explained. As an experiment, the power consumption of the implemented mobile phone under a number of user scenarios has been measured.
A High Swing Range, High Bandwidth CMOS PGA and ADC for IF QPSK Receiver Using 1.8V Supply
Lee, Woo-Yol ; Lim, Jong-Chul ; Park, Hee-Won ; Hong, Kuk-Tae ; Lee, Hyeong-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 5, issue 4, 2005, Pages 276~281
This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth,
gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential
input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is
, sampling freq. is 25MHz), we can process the IF QPSK signal (
) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.