Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 6, Issue 4 - Dec 2006
Volume 6, Issue 3 - Sep 2006
Volume 6, Issue 2 - Jun 2006
Volume 6, Issue 1 - Mar 2006
Selecting the target year
NANOCAD Framework for Simulation of Quantum Effects in Nanoscale MOSFET Devices
Jin, Seong-Hoon ; Park, Chan-Hyeong ; Chung, In-Young ; Park, Young-June ; Min, Hong-Shick ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 1~9
We introduce our in-house program, NANOCAD, for the modeling and simulation of carrier transport in nanoscale MOSFET devices including quantum-mechanical effects, which implements two kinds of modeling approaches: the top-down approach based on the macroscopic quantum correction model and the bottom-up approach based on the microscopic non-equilibrium Green’s function formalism. We briefly review these two approaches and show their applications to the nanoscale bulk MOSFET device and silicon nanowire transistor, respectively.
Schottky Barrier MOSFETs with High Current Drivability for Nano-regime Applications
Jang, Moon-Gyu ; Kim, Yark-Yeon ; Jun, Myung-Sim ; Choi, Chel-Jong ; Kim, Tae-Youb ; Park, Byoung-Chul ; Lee, Seong-Jae ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 10~15
Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from
to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed
saturation current at
= 2V condition (
= 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.
Fabrication of p-type FinFETs with a 20 nm Gate Length using Boron Solid Phase Diffusion Process
Cho, Won-Ju ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 16~21
A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the
junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.
Highly Manufacturable 65nm McFET (Multi-channel Field Effect Transistor) SRAM Cell with Extremely High Performance
Kim, Sung-Min ; Yoon, Eun-Jung ; Kim, Min-Sang ; Li, Ming ; Oh, Chang-Woo ; Lee, Sung-Young ; Yeo, Kyoung-Hwan ; Kim, Sung-Hwan ; Choe, Dong-Uk ; Suk, Sung-Dae ; Kim, Dong-Won ; Park, Dong-Gun ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 22~29
We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as
times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage (
) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.
Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor
Oh, Chang-Woo ; Kim, Sung-Hwan ; Yeo, Kyoung-Hwan ; Kim, Sung-Min ; Kim, Min-Sang ; Choe, Jeong-Dong ; Kim, Dong-Won ; Park, Dong-Gun ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 30~37
In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.
1/f Noise Characteristics of Sub-100 nm MOS Transistors
Lee, Jeong-Hyun ; Kim, Sang-Yun ; Cho, Il-Hyun ; Hwang, Sung-Bo ; Lee, Jong-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 38~42
We report 1/f noise PSD(Power Spectrum Density) of sub-100 nm MOSFETs as a function of various parameters such as HCS (Hot Carrier Stress), bias condition, temperature, device size and types of MOSFETs. The noise spectra of sub-100 nm devices showed Lorentzian-like noise spectra. We could check roughly the position of a dominant noise source by changing
. With increasing measurement temperature, the 1/f noise PSD of 50 nm PMOS device decreases, but there is no decrease in the noise of NMOS device. RTN (Random Telegraph Noise) was measured from the device that shows clearly a Lorentzian-like noise spectrum in 1/f noise spectrum.
Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices
Choi, Woo-Young ; Lee, Jong-Duk ; Park, Byung-Gook ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 43~51
80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3
, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.
Single-Electron Logic Cells and SET/FET Hybrid Integrated Circuits
Kim, S.J. ; Lee, C.K. ; Lee, J.U. ; Choi, S.J. ; Hwang, J.H. ; Lee, S.E. ; Choi, J.B. ; Park, K.S. ; Lee, W.H. ; Paik, I.B. ; Kang, J.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 1, 2006, Pages 52~58
Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.