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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 6, Issue 4 - Dec 2006
Volume 6, Issue 3 - Sep 2006
Volume 6, Issue 2 - Jun 2006
Volume 6, Issue 1 - Mar 2006
Selecting the target year
Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM
Kim, Yong-Sung ; Shin, Soo-Ho ; Han, Sung-Hee ; Yang, Seung-Chul ; Sung, Joon-Ho ; Lee, Dong-Jun ; Lee, Jin-Woo ; Chung, Tae-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 61~67
We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.
Low Voltage Program/Erase Characteristics of Si Nanocrystal Memory with Damascene Gate FinFET on Bulk Si Wafer
Choe, Jeong-Dong ; Yeo, Kyoung-Hwan ; Ahn, Young-Joon ; Lee, Jong-Jin ; Lee, Se-Hoon ; Choi, Byung-Yong ; Sung, Suk-Kang ; Cho, Eun-Suk ; Lee, Choong-Ho ; Kim, Dong-Won ; Chung, Il-Sub ; Park, Dong-Gun ; Ryu, Byung-Il ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 68~73
We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large
shifts over 2.5V at 12V/
for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.
High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library
Kim, Min-Su ; Han, Sang-Shin ; Chae, Kyoung-Kuk ; Kim, Chung-Hee ; Jung, Gun-Ok ; Kim, Kwang-Il ; Park, Jin-Young ; Shin, Young-Min ; Park, Sung-Bae ; Jun, Young-Hyun ; Kong, Bai-Sun ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 74~78
This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.
Effects on Optical Characteristics of GaN Polarity Controlled by Substrate
Kang, Sang-Won ; Shim, Hyun-Wook ; Lee, Dong-Yul ; Han, Sang-Heon ; Kim, Dong-Joon ; Kim, Je-Won ; Oh, Bang-Won ; Kryliouk, Olga ; Anderson, Timothy J. ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 79~86
N-polar, Ga-polar, and non-polar GaN was grown by MBE and MOVPE using various substrates and influence of polarity has been investigated. The GaN growth by MOVPE is along cplane (0001), c-plane (0001), and a-plane (11-20) direction on c-plane (0001), a-plane (11-20) and r-plane (1-102) sapphire substrate respectively. The polarity of the film has a strong influence on the morphology and the optical properties of PA-MBE grown As-doped GaN layers. Strong blue emission from As-doped GaN was observed only in the case of N-polarity (000-1) layers, which was attributed to the highest concentration of Ga dangling bonds for this polarity of a GaN surface.
?Color STN (CSTN) LCD Driver Integrated Circuit with Sense Amplifier of Non-Volatile Memory
Shin, Chang-Hee ; Cho, Ki-Seok ; Lee, Yong-Sup ; Lee, Jae-Hoon ; Sohn, Ki-Sung ; Kwon, Oh-Kyong ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 87~89
This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.
?Growth and Characterization of InGaN/GaN MQWs on Two Different Types of Substrate
Kim, Taek-Sung ; Park, Jae-Young ; Cuong, Tran Viet ; Hong, Chang-Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 90~94
We report on the growth and characterization of InGaN/GaN MQWs on two different types of sapphire substrates and GaN substrates. The InGaN/GaN MQWs are grown by using metalorganic chemical vapor deposition. Our analysis of the satellite peaks in the HRXRD patterns shows, GaN substrates InGaN/GaN MQW compared to sapphire substrates InGaN/GaN MQW, more compressive strain on GaN substrates than on sapphire substrates. However, results of optical investigation of InGaN/GaN MQWs grown on GaN substrates and on sapphire substrates, which have lower Stokes-like shift of PL to GaN substrates compared to sapphire substrates, are shown to the potential fluctuation and the quantum-confined Stark effect induced by the built-in internal field due to spontaneous and straininduced piezoelectric polarizations. The InGaN/GaN MQWs are shown to quantify the Stokes-like shift as a function of x.
Hydrogen Ion Implantation Mechanism in GaAs-on-insulator Wafer Formation by Ion-cut Process
Woo, Hyung-Joo ; Choi, Han-Woo ; Kim, Joon-Kon ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 95~100
The GaAs-on-insulator (GOI) wafer fabrication technique has been developed by using ion-cut process, based on hydrogen ion implantation and wafer direct bonding techniques. The hydrogen ion implantation condition for the ion-cut process in GaAs and the associated implantation mechanism have been investigated in this paper. Depth distribution of hydrogen atoms and the corresponding lattice disorder in (100) GaAs wafers produced by 40 keV hydrogen ion implantation were studied by SIMS and RBS/channeling analysis, respectively. In addition, the formation of platelets in the as-implanted GaAs and their microscopic evolution with annealing in the damaged layer was also studied by cross-sectional TEM analysis. The influence of the ion fluence, the implantation temperature and subsequent annealing on blistering and/or flaking was studied, and the optimum conditions for achieving blistering/splitting only after post-implantation annealing were determined. It was found that the new optimum implant temperature window for the GaAs ion-cut lie in
, which is markedly lower than the previously reported window probably due to the inaccuracy in temperature measurement in most of the other implanters.
Nanoscale Floating-Gate Characteristics of Colloidal Au Nanoparticles Electrostatically Assembled on Si Nanowire Split-Gate Transistors
Jeon, Hyeong-Seok ; Park, Bong-Hyun ; Cho, Chi-Won ; Lim, Chae-Hyun ; Ju, Heong-Kyu ; Kim, Hyun-Suk ; Kim, Sang-Sig ; Lee, Seung-Beck ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 101~105
Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with
nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.
DC Characteristics of P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with
Choi, Sang-Sik ; Yang, Hyun-Duk ; Han, Tae-Hyun ; Cho, Deok-Ho ; Kim, Jea-Yeon ; Shim, Kyu-Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 106~113
Electrical properties of
p-MOSFETs have been exploited in an effort to investigate
channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in
channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide.
channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of
Structure-related Characteristics of SiGe HBT and 2.4 GHz Down-conversion Mixer
Lee, Sang-Heung ; Kim, Sang-Hoon ; Lee, Ja-Yol ; Bae, Hyun-Cheol ; Lee, Seung-Yun ; Kang, Jin-Yeong ; Kim, Bo-Woo ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 114~118
In this paper, the effect of base and collector structures on DC, small signal characteristics of SiGe HBTs fabricated by RPCVD was investigated. The structure of SiGe HBTs was designed into four types as follows: SiGe HBT structures which are standard, apply extrinsic-base SEG selective epitaxial growth (SEG), apply selective collector implantation (SCI), and apply both extrinsic-base SEG and SCI. We verified the devices could be applied to the fabrication of RFIC chip through a fully integrated 2.4 GHz down-conversion mixer.
Fabrication and Characteristics Study of
Ismail, Raid A. ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 2, 2006, Pages 119~123
This work presents the fabrication and characteristics of
heterojunction prepared by rapid thermal oxidation technique without any postdeposition annealing condition. The bismuth trioxide film was deposited onto monocrystalline Si and glass substrates by rapid thermal oxidation of bismuth film with aid of halogen lamp at
s in static air. The structural, optical and electrical properties of
film were investigated and compared with other published results. The structural investigation showed that the grown films are polycrystalline and multiphase (
). Optical properties revealed that these films having direct optical band gap of 2.55 eV at 300 K with high transparency in visible and NIR regions. Dark and illuminated I-V, CV, and spectral responsivity of
heterojunction were investigated and discussed.