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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 6, Issue 4 - Dec 2006
Volume 6, Issue 3 - Sep 2006
Volume 6, Issue 2 - Jun 2006
Volume 6, Issue 1 - Mar 2006
Selecting the target year
A Pipelined Hardware Architecture of an H.264 Deblocking Filter with an Efficient Data Distribution
Lee, Sang-Heon ; Lee, Hyuk-Jae ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 227~233
In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.
A Rule-based Optimal Placement of Scaling Shifts in Floating-point to Fixed-point Conversion for a Fixed-point Processor
Park, Sang-Hyun ; Cho, Doo-San ; Kim, Tae-Song ; Paek, Yun-Heung ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 234~239
In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.
A Bit-level ACSU of High Speed Viterbi Decoder
Kim, Min-Woo ; Cho, Jun-Dong ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 240~245
Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.
An Implementation Method of Cycle Accurate Simulator for the Design of a Pipelined DSP
Park, Hyeong-Bae ; Park, Ju-Sung ; Kim, Tae-Hoon ; Chi, Hua-Jun ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 246~251
In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.
A Low-Power ECC Check Bit Generator Implementation in DRAMs
Cha, Sang-Uhn ; Lee, Yun-Sang ; Yoon, Hong-Il ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 252~256
A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.
Charge Pump Circuits with Low Area and High Power Efficiency for Memory Applications
Kang, Kyeong-Pil ; Min, Kyeong-Sik ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 257~263
New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than
across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the
ratio is 3.5 and
A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process
Chi, Hyung-Joon ; Lee, Jae-Seung ; Sim, Jae-Yoon ; Park, Hong-June ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 264~269
DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is
. It consumes 57mW and occupies 450*325um2 of die area.
A Pseudo Multiple Capture CMOS Image Sensor with RWB Color Filter Array
Park, Ju-Seop ; Choe, Kun-Il ; Cheon, Ji-Min ; Han, Gun-Hee ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 270~274
A color filter array (CFA) helps a single electrical image sensor to recognize color images. The Red-Green-Blue (RGB) Bayer CFA is commonly used, but the amount of the light which arrives at the photodiode is attenuated with this CFA. Red-White-Blue (RWB) CFA increases the amount of the light which arrives at photodiode by using White (W) pixels instead of Green (G) pixels. However, white pixels are saturated earlier than red and blue pixels. The pseudo multiple capture scheme and the corresponding RWB CFA were proposed to overcome the early saturation problem of W pixels. The prototype CMOS image sensor (CIS) was fabricated with
CMOS process. The proposed CIS solves the early saturation problem of W pixels and increases the dynamic range.
Integratable Micro-Doherty Transmitter
Lee, Jae-Ho ; Kim, Do-Hyung ; Burm, Jin-Wook ; Park, Jin-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 275~280
We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.
A 10-GHz CMOS LC VCO with Wide Tuning Range Using Capacitive Degeneration
Yu, Tae-Geun ; Cho, Seong-Ik ; Jeong, Hang-Geun ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 281~285
In order to widen the tuning range, capacitive degeneration is applied to fully CMOS LC VCOs. Small signal analysis shows that the fixed MOSFET capacitance seen by the LC tank is smaller than that of the traditional LC VCO, resulting in significant extension in the tuning range. This improvement in the tuning range has been verified through measurement of a 10-GHz LC VCO fabricated by
CMOS process. The measured tuning range is from 9.8-GHz to 12-GHz, which is better than those of the reported CMOS LC VCOs in 10-GHz band. The measured phase noise is - 103dBc/Hz at 1MHz offset.
A 1.2-V Wide-Band SC Filter for Wireless Communication Transceivers
Yang, Hui-Kwan ; Cha, Sang-Hyun ; Lee, Seung-Yun ; Lee, Sang-Heon ; Lim, Jin-Up ; Choi, Joong-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 286~292
This paper presents the design of a low-voltage wide-band switched-capacitor (SC) filter for wireless communication receiver applications. The filter is the 5th-order Elliptic lowpass filter. With the clock frequency of 50MHz implying that an effective sampling frequency is 100MHz with double sampling scheme, the cut-off frequency of the filter is programmable to be 1.25MHz, 2.5MHz, 5MHz and 10MHz. For low-power systems powered by a single-cell battery, the SC filter was elaborately designed to operate at 1.2V power supply. Simulation result shows that the 3rd-order input intercept point (IIP3) can be up to 27dBm. The filter was fabricated in a
1P5M standard CMOS technology and measured frequency responses show good agreement with the simulation ones. The current consumption is 34mA at a 1.2V power supply.
Thermopiezoelectric Cantilever for Probe-Based Data Storage System
Jang, Seong-Soo ; Jin, Won-Hyeog ; Kim, Young-Sik ; Cho, Il-Joo ; Lee, Dae-Sung ; Nam, Hyo-Jin ; Bu, Jong. U. ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 293~298
Thermopiezoelectric method, using poly silicon heater and a piezoelectric sensor, was proposed for writing and reading in a probe based data storage system. Resistively heated tip writes data bits while scanning over a polymer media and piezoelectric sensor reads data bits from the self-generated charges induced by the deflection of the cantilever. 34
34 array of thermopiezoelectric nitride cantilevers were fabricated by a single step wafer level transfer method. We analyzed the noise level of the charge amplifier and measured the noise signal. With the sensor and the charge amplifier 20mn of deflection could be detected at a frequency of 10KHz. Reading signal was obtained from the cantilever array and the sensitivity was calculated.
A Novel Test Structure for Process Control Monitor for Un-Cooled Bolometer Area Array Detector Technology
Saxena, R.S. ; Bhan, R.K. ; Jalwania, C.R. ; Lomash, S.K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 6, issue 4, 2006, Pages 299~312
This paper presents the results of a novel test structure for process control monitor for uncooled IR detector technology of microbolometer arrays. The proposed test structure is based on resistive network configuration. The theoretical model for resistance of this network has been developed using 'Compensation' and 'Superposition' network theorems. The theoretical results of proposed resistive network have been verified by wired hardware testing as well as using an actual 16x16 networked bolometer array. The proposed structure uses simple two-level metal process and is easy to integrate with standard CMOS process line. The proposed structure can imitate the performance of actual fabricated version of area array closely and it uses only 32 pins instead of 512 using conventional method for a
array. Further, it has been demonstrated that the defective or faulty elements can be identified vividly using extraction matrix, whose values are quite similar(within the error of 0.1%), which verifies the algorithm in small variation case(
variation). For example, an element, intentionally damaged electrically, has been shown to have the difference magnitude much higher than rest of the elements(1.45 a.u. as compared to
0.25 a.u. of others), confirming that it is defective. Further, for the devices having non-uniformity
10%, both the actual non-uniformity and faults are predicted well. Finally, using our analysis, we have been able to grade(pass or fail) 60 actual devices based on quantitative estimation of non-uniformity ranging from ＜ 5% to ＞ 20%. Additionally, we have been able to identify the number of bad elements ranging from 0 to ＞ 15 in above devices.