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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 7, Issue 4 - Dec 2007
Volume 7, Issue 3 - Sep 2007
Volume 7, Issue 2 - Jun 2007
Volume 7, Issue 1 - Mar 2007
Selecting the target year
Minimizing Leakage of Sequential Circuits through Flip-Flop Skewing and Technology Mapping
Heo, Se-Wan ; Shin, Young-Soo ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 215~220
DOI : 10.5573/JSTS.2007.7.4.215
Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.
A New Scan Chain Fault Simulation for Scan Chain Diagnosis
Chun, Sung-Hoon ; Kim, Tae-Jin ; Park, Eun-Sei ; Kang, Sung-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 221~228
DOI : 10.5573/JSTS.2007.7.4.221
In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.
Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing
Wu, Chou-Pin ; Wu, Jen-Ming ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 229~234
DOI : 10.5573/JSTS.2007.7.4.229
In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.
A SSN-Reduced 5Gb/s Parallel Transmitter
Lee, Seon-Kyoo ; Kim, Young-Sang ; Park, Hong-June ; Sim, Jae-Yoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 235~240
DOI : 10.5573/JSTS.2007.7.4.235
A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a
CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.
Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology
Kim, Kyung-Ki ; Kim, Yong-Bin ; Lee, Young-Jun ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 241~246
DOI : 10.5573/JSTS.2007.7.4.241
This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40
MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.
A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions
Ma, Yao ; Song, Yang ; Ikenaga, Takeshi ; Goto, Satoshi ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 247~253
DOI : 10.5573/JSTS.2007.7.4.247
In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the
integer forward and inverse DCT transform matrices, (2) divide them into four
sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of
and matrices of
forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either
transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) (
) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.
Nanochannels for Manipulation of DNA Molecule using Various Fabrication Molecule
Hwang, M.T. ; Cho, Y.H. ; Lee, S.W. ; Takama, N. ; Fujii, T. ; Kim, B.J. ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 254~259
DOI : 10.5573/JSTS.2007.7.4.254
In this report, several fabrication techniques for the formation of various nanochannels (with
, Si, or Quartz) are introduced. Moreover, simple fabrication technique for generating
nanochannels without nanolithography is presented. By using different nanochannels, the degree of stretching DNA molecule will be evaluated. Finally, we introduce a nanometer scale fluidic channel with electrodes on the sidewall of it, to detect and analyze single DNA molecule. The cross sectional shape of the nanotrench is V-groove, which was implemented by thermal oxidation. Electrodes were deposited through both sidewalls of nanotrench and the sealing of channel was done by covering thin poly-dimethiysiloxane (PDMS) polymer sheet.
Signal Transient and Crosstalk Model of Capacitively and Inductively Coupled VLSI Interconnect Lines
Kim, Tae-Hoon ; Kim, Dong-Chul ; Eo, Yung-Seon ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 260~266
DOI : 10.5573/JSTS.2007.7.4.260
Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.
A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-μm CMOS
Shin, Jae-Wook ; Kim, Jong-Sik ; Kim, Seung-Soo ; Shin, Hyun-Chol ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 267~273
DOI : 10.5573/JSTS.2007.7.4.267
A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in
CMOS, the PLL covers
MHz (UHF), and
MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.
Efficiency Improvement of HBT Class E Power Amplifier by Tuning-out Input Capacitance
Kim, Ki-Young ; Kim, Ji-Hoon ; Park, Chul-Soon ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 274~280
DOI : 10.5573/JSTS.2007.7.4.274
This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance (
) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic
affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.
Phase Locked Loop Sub-Circuits for 24 GHz Signal Generation in 0.5μm SiGe HBT technology
Choi, Woo-Yeol ; Kwon, Young-Woo ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 281~286
DOI : 10.5573/JSTS.2007.7.4.281
In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using
SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider.
SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.
Poly-crystalline Silicon Thin Film Transistor: a Two-dimensional Threshold Voltage Analysis using Green's Function Approach
Sehgal, Amit ; Mangla, Tina ; Gupta, Mridula ; Gupta, R.S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 7, issue 4, 2007, Pages 287~298
DOI : 10.5573/JSTS.2007.7.4.287
A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.