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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
JSTS:Journal of Semiconductor Technology and Science
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 9, Issue 4 - Dec 2009
Volume 9, Issue 3 - Sep 2009
Volume 9, Issue 2 - Jun 2009
Volume 9, Issue 1 - Mar 2009
Selecting the target year
Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System
Park, Jang-Woong ; SunWoo, Myung-Hoon ; Kim, Pan-Soo ; Chang, Dae-Ig ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 181~186
DOI : 10.5573/JSTS.2009.9.4.181
This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.
Design of High-Performance Intra Prediction Circuit for H.264 Video Decoder
Yoo, Ji-Hye ; Lee, Seon-Young ; Cho, Kyeong-Soon ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 187~191
DOI : 10.5573/JSTS.2009.9.4.187
This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD (
) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.
A 2.4 /5.2-GHz Dual Band CMOS VCO using Balanced Frequency Doubler with Gate Bias Matching Network
Choi, Sung-Sun ; Yu, Han-Yeol ; Kim, Yong-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 192~197
DOI : 10.5573/JSTS.2009.9.4.192
This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in
CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is
Design of a Reliable Broadband I/O Employing T-coil
Kim, Seok ; Kim, Shin-Ae ; Jung, Goeun ; Kwon, Kee-Won ; Chun, Jung-Hoon ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 198~204
DOI : 10.5573/JSTS.2009.9.4.198
Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.
A MAS Information Management Method for WiMedia MAC Protocol
Chung, Tae-Wook ; Chung, Chul-Ho ; Kim, Jae-Seok ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 205~208
DOI : 10.5573/JSTS.2009.9.4.205
In this paper, a MAS information management method is proposed for the WiMedia MAC protocol. WiMedia MAC configures a fully distributed network based on Ad-hoc method. WiMedia devices communicate during Superframe which is a communication unit in WiMedia MAC. Each superframe which consist of 256 MASs is divided into two periods, beacon period and data period. In data period, devices communicate with each other using the received channel access information during the beacon period. Due to only
timing allowance between beacon period and data period, the process of the MAS information management cannot be completed in time if entire process handle by software. Therefore, we propose a novel MAS information management method using hardware module. With our proposed method, a WiMedia device is satisfied with the processing time that is required in WiMedia MAC protocol.
Library-based Mapping of Application to Reconfigurable Array Architecture
Han, Kyu-Seung ; Choi, Ki-Young ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 209~215
DOI : 10.5573/JSTS.2009.9.4.209
Reconfigurable array architecture is recently attracting much attention. It is a flexible hardware architecture, which can dynamically change its configuration to execute various functions while maintainning high performance. However, pursuing flexibility and performance at the same time leads to complexity, thereby makes the mapping of applications a difficult process. There have been attempts to use compiler or high level synthesis techniques to solve the problem. In this paper, we propose yet another method, which uses libraries for the mapping to provide an abstracttion of the internal structure and at the same time to reduce the development time and efforts through the automated process. We have selected a JPEG decoder as an example to apply the proposed method. As a result, we obtained about 20% less performance compared to manual mapping but development time is dramatically reduced to less than 1%.
Comparison of Circuit Reduction Techniques for Power Network Noise Analysis
Kim, Jin-Wook ; Kim, Young-Hwan ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 216~224
DOI : 10.5573/JSTS.2009.9.4.216
The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.
Symmetric and Asymmetric Double Gate MOSFET Modeling
Abebe, H. ; Cumberbatch, E. ; Morris, H. ; Tyree, V. ; Numata, T. ; Uno, S. ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 225~232
DOI : 10.5573/JSTS.2009.9.4.225
An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DG-MOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.
Mixed CT/DT Cascaded Sigma-Delta Modulator
Lee, Kye-Shin ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 233~239
DOI : 10.5573/JSTS.2009.9.4.233
A mixed CT/DT 2-1 cascaded
which includes a first stage CT
and a second stage mismatch insensitive two-channel time-interleaved DT
is proposed. With this approach, the advantages of both CT and DT
including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The two-channel time-interleaved
used in the second stage alleviates the speed constraints of the DT
, whereas enables better matching between the analog and digital filter coefficients compared to CT
Introduction to Industrial Applications of Low Power Design Methodologies
Kim, Hyung-Ock ; Lee, Bong-Hyun ; Choi, Jung-Yon ; Won, Hyo-Sig ; Choi, Kyu-Myung ; Kim, Hyun-Woo ; Lee, Seung-Chul ; Hwang, Seung-Ho ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 240~248
DOI : 10.5573/JSTS.2009.9.4.240
Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-
metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.
Power Amplifiers and Transmitters for Next Generation Mobile Handsets
Choi, Jin-Sung ; Kang, Dae-Hyun ; Kim, Dong-Su ; Park, Jung-Min ; Jin, Bo-Shi ; Kim, Bum-Man ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 249~256
DOI : 10.5573/JSTS.2009.9.4.249
As a wireless handset deals with multiple application standards concurrently, RF transmitters and power amplifiers are required to be more power efficient and reconfigurable. In this paper, we review the recent advances in the design of the power amplifiers and transmitters. Then, the systematic design approaches to improve the performance with the digital baseband signal processing are introduced for the next generation mobile handset.
RF CMOS Power Amplifiers for Mobile Terminals
Son, Ki-Yong ; Koo, Bon-Hoon ; Lee, Yu-Mi ; Lee, Hong-Tak ; Hong, Song-Cheol ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 257~265
DOI : 10.5573/JSTS.2009.9.4.257
Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiersin the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.
Effects of Rapid Thermal Annealing Temperature on Performances of Nanoscale FinFETs
Sengupta, M. ; Chattopadhyay, S. ; Maiti, C.K. ;
JSTS:Journal of Semiconductor Technology and Science, volume 9, issue 4, 2009, Pages 266~272
DOI : 10.5573/JSTS.2009.9.4.266
In the present work three dimensional process and device simulations were employed to study the performance variations with RTA. It is observed that with the increase in RTA temperature, the arsenic dopants from the source /drain region diffuse laterally under the spacer region and simultaneously acceptors (Boron) are redistributed from the central axis region of the fin towards the Si/SiO2 interface. As a consequence both drive current and peak cut-off frequency of an n-FinFET are observed to improve with RTA temperatures. Volume inversion and hence the flow of carries through the central axis region of the fin due to reduced scattering was found behind the performance improvements with increasing RTA temperature.