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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
IEIE Transactions on Smart Processing and Computing
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 3, Issue 6 - Dec 2014
Volume 3, Issue 5 - Oct 2014
Volume 3, Issue 4 - Aug 2014
Volume 3, Issue 3 - Jun 2014
Volume 3, Issue 2 - Apr 2014
Volume 3, Issue 1 - Feb 2014
Selecting the target year
Detection of Edges in Color Images
Ganchimeg, Ganbold ; Turbat, Renchin ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 345~352
DOI : 10.5573/IEIESPC.2014.3.6.345
Edge detection considers the important technical details of digital image processing. Many edge detection operators already perform edge detection in digital color imaging. In this study, the edge of many real color images that represent the type of digital image was detected using a new operator in the least square approximation method, which is a type of numerical method. The Linear Fitting algorithm is computationally more expensive compared to the Canny, LoG, Sobel, Prewitt, HIS, Fuzzy, Parametric, Synthetic and Vector methods, and Robert' operators. The results showed that the new method can detect an edge in a digital color image with high efficiency compared to standard methods used for edge detection. In addition, the suggested operator is very useful for detecting the edge in a digital color image.
High Performance and FPGA Implementation of Scalable Video Encoder
Park, Seongmo ; Kim, Hyunmi ; Byun, Kyungjin ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 353~357
DOI : 10.5573/IEIESPC.2014.3.6.353
This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD(
), and D1(
) at 266MHz.
Flickering Effect Reduction Based on the Modified Transformation Function for Video Contrast Enhancement
Yang, Hyeonseok ; Park, Jinwook ; Moon, Youngshik ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 358~365
DOI : 10.5573/IEIESPC.2014.3.6.358
This paper proposes a method that reduces the flickering effect caused by A-GLG (Adaptive Gray-Level Grouping) during video contrast enhancement. Of the GLG series, A-GLG shows the best contrast enhancement performance. The GLG series is based on histogram grouping. Histogram grouping is calculated differently between the continuous frames with a similar histogram and causes a subtle change in the transformation function. This is the reason for flickering effect when the video contrast is enhanced by A-GLG. To reduce the flickering effect caused by A-GLG, the proposed method calculates a modified transformation function. The modified transformation function is calculated using a previous and current transformation function applied with a weight separately. The proposed method was compared with A-GLG for flickering effect reduction and video contrast enhancement. Through the experimental results, the proposed method showed not only a reduced flickering effect, but also video contrast enhancement.
Wild Image Object Detection using a Pretrained Convolutional Neural Network
Park, Sejin ; Moon, Young Shik ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 366~371
DOI : 10.5573/IEIESPC.2014.3.6.366
This paper reports a machine learning approach for image object detection. Object detection and localization in a wild image, such as a STL-10 image dataset, is very difficult to implement using the traditional computer vision method. A convolutional neural network is a good approach for such wild image object detection. This paper presents an object detection application using a convolutional neural network with pretrained feature vector. This is a very simple and well organized hierarchical object abstraction model.
Parameter Estimation of Linear-FM with Modified sMLE for Radar Signal Active Cancelation Application
Choi, Seungkyu ; Lee, Chungyong ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 372~381
DOI : 10.5573/IEIESPC.2014.3.6.372
This study examined a radar signal active cancelation technique, which is a theoretical way of achieving stealth by employing a baseband process that involves sampling the incoming hostile radar signal, analyzing its characteristics, and generating countermeasure signals to cancel out the linear-FM signal of the hostile radar signal reflected from the airborne target. To successfully perform an active cancelation, the effects of errors in the countermeasure signal were first analyzed. To generate the countermeasure signal that requires very fast and accurate processing, the down-sampling technique with the suboptimal maximum likelihood estimation (sMLE) scheme was proposed to improve the speed of the estimation process while preserving the estimation accuracy. The simulation results showed that the proposed down-sampling technique using a 2048 FFT size yields substantial power reduction despite its small FFT size and exhibits similar performance to the sMLE scheme using the 32768 FFT size.
Computational Approach to Color Overlapped Integral Imaging for Depth Estimation
Lee, Eunsung ; Lim, Joohyun ; Kim, Sangjin ; Har, Donghwan ; Paik, Joonki ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 382~387
DOI : 10.5573/IEIESPC.2014.3.6.382
A computational approach to depth estimations using a color over lapped integral imaging system is presented. The proposed imaging system acquires multiple color images simultaneously through a single lens with an array of multiple pinholes that are distributed around the optical axis. This paper proposes a computational model of the relationship between the real distance of an object and the disparity among different color images. The proposed model can serve as a computational basis of a single camera-based depth estimation.
Early Termination of Block Vector Search for Fast Encoding of HEVC Screen Content Coding
Ma, Jonghyun ; Sim, Donggyu ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 388~392
DOI : 10.5573/IEIESPC.2014.3.6.388
This paper proposes an early termination method of a block vector search for fast encoding of high efficiency video coding (HEVC) screen content coding (SCC). In the proposed algorithm, two blocks indicated by two block vector predictors (BVPs) were first employed as an intra block copy (IBC) search. If the sum of absolute difference (SAD) value of the block is less than a threshold defined empirically, an IBC BV search is terminated early. The initial threshold for early termination is derived by statistical analysis and it can be modified adaptively based on a quantization parameter (QP). The proposed algorithm is evaluated on SCM-2.0 under all intra (AI) coding configurations. Experimental results show that the proposed algorithm reduces IBC BV search time by 29.23% on average while the average BD-rate loss is 0.41% under the HEVC SCC common test conditions (CTC).
Lee, Wonjun ; Na, Yeoul ; Kim, Seon Wook ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 393~396
DOI : 10.5573/IEIESPC.2014.3.6.393
Integer-Pel Motion Estimation for HEVC on Compute Unified Device Architecture (CUDA)
Lee, Dongkyu ; Sim, Donggyu ; Oh, Seoung-Jun ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 397~403
DOI : 10.5573/IEIESPC.2014.3.6.397
A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.
High accuracy, Low Power Spread Spectrum Clock Generator to Reduce EMI for Automotive Applications
Lee, Dongsoo ; Choi, Jinwook ; Oh, Seongjin ; Kim, SangYun ; Lee, Kang-Yoon ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 404~409
DOI : 10.5573/IEIESPC.2014.3.6.404
This paper presents a Spread Spectrum Clock Generator (SSCG) based on Relaxation oscillator using Up/Down Counter. The current is controlled by a counter and the spread spectrum of the Relaxation Oscillator. A Relaxation Oscillator with temperature compensation using the BGR and ADC is presented. The current to determine the frequency of the Relaxation Oscillator can be controlled. The output frequency of the temperature can be compensated by adjusting the current according to the temperature using the code that is the output from the ADC and BGR. EMI Reduction of SSCG is 11 dB, and Spread down frequency is 150 kHz. The current consumption is
from 5V and the operating frequency is from 2.3 MHz to 5.75 MHz. The rate of change of the output frequency with temperature was approximately
. The SSCG is fabricated in a 0.35um CMOS process with active area
A High Efficiency Active Rectifier for 6.78MHz Wireless Power Transfer Receiver with Bootstrapping Technique and All Digital Delay-Locked Loop
Nga, Truong Thi Kim ; Park, Hyung-Gu ; Lee, Kang-Yoon ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 410~415
DOI : 10.5573/IEIESPC.2014.3.6.410
This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS
technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.
A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology
Abbasizadeh, Hamed ; Rikan, Behnam Samadpoor ; Lee, Dong-Soo ; Hayder, Abbas Syed ; Lee, Kang-Yoon ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 416~424
DOI : 10.5573/IEIESPC.2014.3.6.416
This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.
High Efficiency Buck-Converter with Short Circuit Protection
Cho, Han-Hee ; Park, Kyeong-Hyeon ; Cho, Sang-Woon ; Koo, Yong-Seo ;
IEIE Transactions on Smart Processing and Computing, volume 3, issue 6, 2014, Pages 425~429
DOI : 10.5573/IEIESPC.2014.3.6.425
This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.